Datasheet

C28 Read/Write
M3 Read/Write
/1
/2
/4
/8*
OSCCLK
* Default at reset
** Semaphore request write
System
PLL
0*
1
PLLSYSCLK
150 MHz Max
M3 Read/Write
C28 Read Only**
XPLLCLKOUT Pin
/1
/2
/4*
Master (M3)
Subsystem
100 MHz Max
/1
/2
/4*
Control (C28)
Subsystem
150 MHz Max
on*
off
0
/1
37.5 MHz Max
Analog
off
/1
/2
/4
/8*
X2
X1
XTAL
XTAL OSC
0*
1
0
XCLKIN
X1/X2 Ext. XTAL 4 – 20 MHz
X1 Ext. CLK source up to 30 MHz
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Figure 3-11. System Clock/PLL
Copyright © 2012–2014, Texas Instruments Incorporated Device Overview 57
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