Datasheet

M3SSCLK
XCLKIN
DSDIVOVRIDEDSOSCSRC
32KHZCLK
INTERNAL
OSC
OSCCLK
10MHZCLK
MAIN
PLL
/2
X2
X1
M3 CPU
HCLKFCLK
SLEEPDEEP
M3CLKENBx
EPI
I C (2)
2
SSI (4)
UART (5)
USB + PHY
(OTG)
EMAC
GP TIMER (4)
uCRC
WDOG 0
NMI WDOG
WDOG 1
CAN
1,2
USB
PLL
GPIO_MUX1
/1
/2
…
/16
/1
/2
/4
uDMA
OSCCLK
SYSDIVSEL
M3SSCLK
M3DEEPSLEEP
ENABLE
CLOCK MODE
PERIPHERAL
CLOCK
ENABLES
RCC REG
RCGC REG
SCGS REG
M3RUN
M3SLEEP
M3DSDIVCLK
M3DEEPSLEEP
SYSCTRL REG
M3SSDIVSEL REG
M3SSDIVSEL
DCGC REG
DSLPCLKCFG REG
ACG (Auto Clock Gate)
M3SSCLK
execution of WFI or WFE instr
activates low power modes
10MHZCLK
32KHZCLK
OSCCLK
DC REG
PLL
DIS
OSCCLK
XCLKIN
OSCCLK
OSCCLK
USBPLLCLK
MISSING
CLK DETECT
XCLKIN
INTR
NVIC
10MHZCLK
M3SSCLK
M3CLKENBx
CONTROL SUBSYSTEM
PLL
DIS
M3 NMI
CLOCKFAIL
MAIN OSC
10MHZCLK
CLOCKFAIL OSCCLK
CLOCKFAIL
( GLOBAL PERIPHERAL ENABLES )
( CLOCK GATING – RUN )
( CLOCK GATING – SLEEP )
( CLOCK GATING – DEEP SLEEP )
M3SSCLK
REGISTER
ACCESS
REGISTER
ACCESS
PERIPH
LOGIC
M3SSCLK
SHARED
RESOURCES
IPC
PERIPH
LOGIC
CLOCKS
CLPMSTAT REG
SHARED
RAMS
MSG
RAMS
OFF
1
0
PLLSYSCLK
1
0
0
1
OSCCLK
ENTER A LOW POWER MODE
SELECTS TYPE
OF WAKEUP
SELECTS BETWEEN SLEEP
AND DEEP SLEEP MODES
ASSERT ANY INTERRUPT
TO EXIT SLEEP OR DEEP SLEEP
SYSPLLCTL REG
SYSPLLSTAT REG
SYSPLLMULT REG
SYSDIVSEL REG
MCLKREQUEST REG
M3SSCLK
/1
/2
/4
/8
SLEEPEXIT
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
Figure 3-10. Cortex-M3 Clocks and Low-Power Modes
56 Device Overview Copyright © 2012–2014, Texas Instruments Incorporated
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