Datasheet

MAIN
OSC
INTEGER
MULTIPLIER
FRACTIONAL
MULTIPLIER
PIN
X1
UPLLMULT REG
/4
USB PLL
000000 : x 1
000001 : x 1
000010 : x 2
000011 : x 3
.
.
.
111101: x 61
111110: x 62
111111: x 63
EXAMPLE 1: X1 OR XCLKIN = 60 MHZ UPLLIMULT = 000000 ( BYPASS PLL) N/A PLLSYSCLK = 60 MHz
EXAMPLE 2: X1 OR XCLKIN = 10 MHz UPLLIMULT = 011000 ( x 24 ) UPLLFMULT = 00 ( NOT USED) PLLSYSCLK = ( 10 x 24) / 4 = 60 MHz
EXAMPLE 3: X1 OR XCLKIN = 64 MHz UPLLIMULT = 000011 ( x 3) UPLLFMULT = 11 ( x 0.75) PLLSYSCLK = ( 64 x 3.75 ) / 4 = 60 MHz
UPLLIMULT UPLLFMULT
0
1
USBPLLCLK
OUPUT OF
THE USB PLL
IS ALWAYS
DIVIDED BY 4
00: NOT USED
01: x 0.25
10: x 0.50
11: x 0.75
6 2
OSCCLK
(1) OUPUT OF THE USB PLL MUST BE ALWAYS 240MHz ( SO THAT USBPLLCLK IS 60MHZ )
PIN
XCLKIN
XCLKIN
PLLINP
UPLLCLKSRC
0
1
UPLLCTL REG
UPLLCLKENUPLLEN
(2)
(2) WHEN UPLLEN BIT = 0, THE USB PLL IS POWERED OFF
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
Figure 3-9. USB PLL
52 Device Overview Copyright © 2012–2014, Texas Instruments Incorporated
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