Datasheet

PIN
‘0’
DE-GLITCH
XRS
RESETS
POWER-ON-RESET
(DIGITAL SUBSYSTEM)
M3
NVIC
M3 WDOGS
(0,1)
DIGITAL LOGIC
(DIGITAL SUBSYSTEM)
1.2V VREG
(DIGITAL SUBSYSTEM)
‘0’
DE-GLITCH
ARS
1.8V VREG
(ANALOG SUBSYSTEM)
XRS
PIN
ARS
1.2V
SUPPLY
PINS
3.3V
SUPPLY
PINS
1.8V
SUPPLY
PINS
DIGITAL LOGIC
(ANALOG SUBSYSTEM)
1.8V 1.2V
3.3V
VREG12EN
PIN
VREG18EN
PIN
CONCERTO
DEVICE
ANALOG SUBSYSTEM GPIOS
DIGITAL SUBSYSTEM GPIOS
CONNECT THE 2 RESET PINS EXTERNALLY THROUGH A BOARD TRACE
1.8V 1.2V
1.8V 1.2V
I/OI/O
3.3V 3.3V
TRISTATE TRISTATE
POR
3.3V
POR
1.8V
POR
POWER-ON-RESET
(ANALOG SUBSYSTEM)
M3WDOGS
POR
1.2V
POR
3.3V
POR
CRESCNF REG
ACIBRST
CONTROL
SUB-
SYSTEM
M3RSNIN
M3 NMI
M3 NMI
WDOG
M3 CPU
RST
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Figure 3-6. Voltage Regulation and Monitoring
Copyright © 2012–2014, Texas Instruments Incorporated Device Overview 43
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