Datasheet

ARS
PIN
M3
NMI
WDOG
M3
SUBSYSTEM
M3
CPU
M3
NVIC
M3 WDOG (0)
M3 WDOG (1)
M3DBGRST
M3SWRST
SHARED
RESOURCES
ANALOG
SUBSYSTEM
C28x
NMI
WDOG
C28x
CPU
C28x
SUBSYSTEM
M3SYSRST
‘0’
DEGLITCH
SYNC
M3WDOGS
XRS
PIN
M3SSCLK
ARS
PIN
DC REG
POR
XRS
XRS
XRS
ACIBRST
SRXRST
M3SYSRST
M3PORRST
C28RSTIN
POR
C28SYSRST
RESET INPUT SIGNAL STATUS
XRS( SETS DEFAULT VALUES )
FLASH PUMP
XRS
CRESCNF REG
DEVICECNF REG
CRESSTS REG
C28SYSRST
C28NMIWD
M3WDOGS
ACIBRST
M3RSNIN
SOFTWARE
JTAG
CONTROLLER
MRESC REG
CONTAINS RESET CAUSES
PERIPHERAL SOFTWARE RESETS
ACIBRST
SRCR REG
GLOBAL PERIPHERAL ENABLES
XRS
GPIO_MUX
C28x BIST
M3 BIST
MLBISTRST
CLBISTRST
VOLTAGE
REGULATION
AND
POWER-ON-RESET
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
Figure 3-5. Resets
38 Device Overview Copyright © 2012–2014, Texas Instruments Incorporated
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Product Folder Links: F28M36P63C F28M36P53C F28M36H53C F28M36H53B F28M36H33C F28M36H33B