Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B

SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014

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3.5 Analog Subsystem

The Analog Subsystem has ADC1, ADC2, and six Analog Comparator + DAC units that can be accessed

via the Analog Common Interface Bus. The ADC Result Registers are accessible by CPUs and DMAs of

the Master and Control Subsystems. All other Analog Peripheral Registers are accessible by the C28x

CPU only. The C28x CPU accesses the ACIB through the C28x Memory Bus, and the C28x DMA through

the C28x DMA Bus. The ACIB arbitrates for access to ADC and Analog Comparator registers between

CPU/DMA bus cycles of the C28x Subsystem with those of the Cortex-M3 Subsystem. In addition to

managing bus cycles, the ACIB also transfers Start-Of-Conversion triggers to the Analog Subsystem and

returns End-Of-Conversion ADC interrupts to both the Master Subsystem and the Control Subsystem.

There are 22 possible Start-Of-Conversion (SOC) sources from the C28x Subsystem that are mapped to a

total of 8 possible SOC triggers inside the Analog Subsystem (to ADC1 and ADC2).

Going the other way, eight End-Of-Conversion (EOC) sources from ADC1 and eight EOC sources from

ADC2 are AND-ed together to form eight interrupts going to destinations in both the Master and Control

Subsystems. Inside the C28x Subsystem, all eight EOC interrupts go to the PIE, but only four of the same

eight go to the C28x DMA.

The Concerto MCU Analog Subsystem has two independent Analog-to-Digital Converters (ADC1, ADC2);

six Analog Comparators + DAC units; and an ACIB to facilitate analog data communications with

Concerto’s two digital subsystems (Cortex-M3 and C28x).

Figure 3-3 shows the Analog Subsystem.

3.5.1 ADC1

The ADC1 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which

12 are currently pinned out. The analog channels are internally pre-assigned to two Sample-and-Hold

(S/H) units A and B, both feeding an Analog Mux whose output is converted to a 12-bit digital value and

stored in ADC1 result registers. The two S/H units enable simultaneous sampling of two analog signals at

a time. Additional channels or channel pairs are converted sequentially. SOC triggers from the Control

Subsystem initiate analog-to-digital conversions. EOC interrupts from ADCs notify the Master and Control

Subsystems that the conversion results are ready to be read from ADC1 result registers.

See Section 7.1.1 for more information on ADC peripherals.

3.5.2 ADC2

The ADC2 consists of a 12-bit Analog-to-Digital converter with up to 16 analog input channels of which

12 are currently pinned out. The analog channels are internally preassigned to two S/H units A and B,

both feeding an Analog Mux whose output is converted to a 12-bit digital value and stored in the ADC2

result registers. The two S/H units enable simultaneous sampling of two analog signals at a time.

Additional channels or channel pairs are converted sequentially. SOC triggers from the Control Subsystem

initiate analog-to-digital conversions. EOC interrupts from ADCs notify the Master and Control Subsystems

that the conversion results are ready to be read from ADC2 result registers.

See Section 7.1.1 for more information on ADC peripherals.

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