Datasheet

C9-C15
RAM
7 x 8 KB
(parity)
C2-C8
RAM
7 x 8 KB
(parity)
SECURE
FLASH
1 MB
(ECC)
BOOT
ROM
64 KB
GPIO_MUX1
GP TIMER (4)
uCRC
I C (2)
2
SSI (4)
UART (5)
USB+PHY (OTG)
EMAC
WDOG (2)
NMI WDOG
SECURE
C1
RAM
8 KB
(ECC)
SECURE
C0
RAM
8 KB
(ECC)
AHB BUS
APB BUS
S0-S7 SHARED RAM (parity)
S0
8 KB
S1
8 KB
S2
8 KB
S3
8 KB
S4
8 KB
S5
8 KB
S6
8 KB
S7
8 KB
MTOC
MSG
RAM
(parity)
2 KB
CTOM
MSG
RAM
(parity)
2 KB
IPC
INTER-
PROC
COMM
M3 SYSTEM BUS
uDMA BUS
L3
RAM
8 KB
(parity)
L2
RAM
8 KB
(parity)
SECURE
FLASH
512 KB
(ECC)
BOOT
ROM
64 KB
SECURE
L1
RAM
8 KB
(ECC)
SECURE
L0
RAM
8 KB
(ECC)
TIMER (3)
XINT (3)
EPWM (12)
NMI WDOG
EQEP (3)
ECAP (6)
McBSP
I C
2
SCI
SPI
GPIO_MUX1
M1
RAM
2 KB
(ECC)
M0
RAM
2 KB
(ECC)
C28 CPU BUS
C28 DMA BUS
16-
BIT
PF2
32-
BIT
PF1
32-
BIT
PF3
C28 CPU
C28
FPU
C28
VCU
C28
DMA
M3 CPU
NVIC
MPU
M3
BUS
MATRIX
M3
uDMA
I-CODE BUS
D-CODE BUS
136 PINS
REGS
ONLY
PIE
ADC_1
MODULE
ADC_2
MODULE
GPIO_MUX2
12 PINS
AIO_MUX2
AIO_MUX1
12 PINS
16/32
- BIT
PF0
8 PINS
ANALOG
SUBSYSTEM
6
COMP
INPUTS
6
COMP
INPUTS
12
ADC
INPUTS
6
COMP
OUT
PUTS
12
ADC
INPUTS
6
COMPARE
+ DAC
UNITS
MEM32
TO AHB
BUS
BRIDGE
ANALOG COMMON INTERFACE BUS
1.2V
VREG
1.8V
VREG
C28 CPU/DMA
ACCESS TO EPI
EPI
INTER-
PROC
COMM
CAN (2)
RESETS
NMI
CLOCKS
SECURITY
DEBUG
FREQ
GASKET
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
1.4 Functional Block Diagram
Figure 1-1. Functional Block Diagram
Copyright © 2012–2014, Texas Instruments Incorporated Device Summary 3
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