Datasheet

EMUSTOP
TIMER (3)
XINT (3)
EPWM
(12)
NMI
WDOG
EQEP (3)
ECAP (6)
McBSP
I C
2
SCI
SPI
PIE (PERIPHERAL INTERRUPT EXPANSION)
C28x
DMA
ANALOG
SUBSYSTEM
GPIO_MUX1
GPIO_MUX1
C28x NMI
EQEP
ERR
SOC TRIGGERS
EOC INTERRUPTS
ADCINT (8:1)
DINTCH (6:1)
TINT 0,1,2
ADCINT (4:1)
GPTRIP
(12:1)
GPTRIP
(12:7)
GPTRIP
(6:4)
PIENMIERR
C28NMIRST
C28 CPU BUS
C28 DMA BUS
C28x
CPU
C28x
FPU
C28x
VCU
PIEINTRS (12:1)
C28x LOCAL MEMORY
TINT1
TINT2
C28NMIINTC28NMI
BOOT
ROM
L2/L3
RAM
(parity)
SECURE
FLASH
(ECC)
SECURE
L0/L1
RAM
(ECC)
RAMUNCERR
RAMACCVIOL
FLASHUNCERR
S0-S7
SHARED
RAM
(parity)
MTOC
MSG
RAM
(parity)
IPC
REGS
CTOM
MSG
RAM
(parity)
MASTER SUBSYSTEM
M0/M1
RAM
(ECC)
C28x NMI
LUFLVF
FLFSM
FLSINGERR RAMSINGERR
MTOCIPC (4:1)
SHARED RESOURCES
GPIO_MUX1
XINT 1,2,3
MXINTA, MRINTA
SOCA (9:1), SOCB(9:1)SOCA (9:1), SOCB(9:1)
TINT 0,1,2
XINT 2
ECCDBLERR
ECCDBLERR
LPMWAKE
M3 NMI
C28x PERIPHERALS
RAMUNCERR
M3 CLOCKS
CLOCKFAIL
LPM WAKEUP
RESETS
EPWM(12:1)TZINT
EPWM(12:1)INT
EQEP(3:1)INT
ECAP(6:1)INT
SPIRXINTA, SPITXINTA
SCIRXINTA, SCITXINTA
GPIO_MUX1
SOCBOSOCAO SYNCO
PERIPHERAL
I/O s
FREQ
GASKET
BUS
BRIDGE
EPI
I2CINT1A, I2CINT2A
GPI (63:0)
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
Figure 3-2. Control Subsystem
28 Device Overview Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: F28M36P63C F28M36P53C F28M36H53C F28M36H53B F28M36H33C F28M36H33B