Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Table 3-15. Interrupts from NVIC to Cortex-M3 (continued)
Interrupt Number
Vector Number Vector Address or Offset Description
(Bit in Interrupt Registers)
132 148 0x0000.0250 GPIO Port R
133 149 0x0000.0254 GPIO Port S
Table 3-16. Exceptions from Cortex-M3 Core to NVIC
Vector Address or
Exception Type Priority
(1)
Vector Number Activation
Offset
Stack top is loaded from
– – 0 0x0000.0000 the first entry of the vector
table on reset.
Reset –3 (highest) 1 0x0000.0004 Asynchronous
Asynchronous
On Concerto devices
activated by clock fail
Non-Maskable Interrupt
–2 2 0x0000.0008 condition, C28 PIE error,
(NMI)
external M3GPIO NMI
input signal, and C28 NMI
WD timeout reset.
Hard Fault –1 3 0x0000.000C –
Memory Management programmable 4 0x0000.0010 Synchronous
Synchronous when
precise and asynchronous
when imprecise.
On Concerto devices
Bus Fault programmable 5 0x0000.0014
activated by memory
access errors and RAM
and flash uncorrectable
data errors.
Usage Fault programmable 6 0x0000.0018 Synchronous
– – 7–10 – Reserved
SVCall programmable 11 0x0000.002C Synchronous
Debug Monitor programmable 12 0x0000.0030 Synchronous
– – 13 – Reserved
PendSV programmable 14 0x0000.0038 Asynchronous
SysTick programmable 15 0x0000.003C Asynchronous
Interrupts programmable 16 and above 0x0000.0040 and above Asynchronous
(1) 0 is the default priority for all the programmable priorities
Copyright © 2012–2014, Texas Instruments Incorporated Device Overview 25
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