Datasheet

GPIO_MUX1
MRINTA
INTR
C28x PIE
C28x
CPU
ALL REG
ACCESS
SYSTEM
CONTROL
REGISTERS
C28CLKIN
C28SYSCLK
MCBSPA_ENCLK
MASTER
SUBSYSTEM
C28LSPCLK
/1
/2
/4
…
/14
MXINTA
REG
ACCESS
PIN
MFSRA
MCLKRA
PIN
MDRA
PIN
PIN
MFSXA
MCLKXA
PIN
MDXA
PIN
C28
DMA
DRR / DXR
REG ACCESS
DRR1 REG DRR2 REG
DXR2 REG DXR1 REG
EXPAND
COMPRESS
RBR REG RSR REG
XSR REG
SPCR2 REG SPCR1 REG
SRGR2 REG SRGR1 REG
SPCR2 REG SPCR1 REG
XCR2 REG XCR1 REG
GENERATION AND CONTROL
OF CLOCK AND FRAME SYNC
PERIPH
LOGIC
RX/TX
INTERRUPT
LOGIC
MFFINT REG
MCR2 REG RCERA REG
RCERB REG
RCERC REG
RCERD REG
RCERE REG
RCERF REG
RCERG REG
RCERH REG
XCERA REG
XCERB REG
XCERC REG
XCERD REG
XCERE REG
XCERF REG
XCERG REG
XCERH REG
MCR1 REG
PCR REG
MULTI -
CHANNEL
SELECTION
MCBSP
(128 CHAN)
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
Figure 7-46. McBSP (C28x)
238 Peripheral Information and Timings Copyright © 2012–2014, Texas Instruments Incorporated
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Product Folder Links: F28M36P63C F28M36P53C F28M36H53C F28M36H53B F28M36H33C F28M36H33B