Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B

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SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014

McBSP features include:

• Full-duplex communication

• Double-buffered transmission and triple-buffered reception, allowing a continuous data stream

• Independent clocking and framing for reception and transmission

• The capability to send interrupts to the CPU and to send DMA events to the DMA controller

• 128 channels for transmission and reception

• Multichannel selection modes that enable or disable block transfers in each of the channels

• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially

connected A/D and D/A devices

• Support for external generation of clock signals and frame-synchronization signals

• A programmable sample rate generator for internal generation and control of clock signals and frame

synchronization signals

• Programmable polarity for frame-synchronization pulses and clock signals

• Direct interface to:

– T1/E1 framers

– IOM-2 compliant devices

– AC97-compliant devices (the necessary multi-phase frame capability is provided)

– I2S compliant devices

– SPI devices

• A wide selection of data sizes: 8, 12, 16, 20, 24, and 32 bits

NOTE

A value of the chosen data size is referred to as a serial word or word in this section.

Elsewhere, word is used to describe a 16-bit value.

• µ-law and A-law companding

• The option of transmitting/receiving 8-bit data with the LSB first

• Status bits for flagging exception/error conditions

• ABIS mode is not supported

Figure 7-46 shows the C28x McBSP peripheral.

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