Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
3.3.2 Cortex-M3 DMA and NVIC
The Cortex-M3 direct memory access (µDMA) module provides a hardware method of transferring data
between peripherals, between memory, and between peripherals and memory without intervention from
the Cortex-M3 CPU. The NVIC manages and prioritizes interrupt handling for the Cortex-M3 CPU.
The Cortex-M3 peripherals use REQ/DONE handshaking to coordinate data transfer requests with the
µDMA. If a DMA channel is enabled for a given peripheral, REQ/DONE from the peripheral will trigger the
data transfer, following which an IRQ request may be sent from the µDMA to the NVIC to announce to the
Cortex-M3 that the transfer has completed. If a DMA channel is not enabled for a given peripheral,
REQ/DONE will directly drive IRQ to the NVIC so that the Cortex-M3 CPU can transfer the data. For those
peripherals that are not supported by the µDMA, IRQs are supplied directly to the NVIC, bypassing the
DMA. This case is true for both Watchdogs, CANs, I
2
Cs, and the Analog-to-Digital Converters sending
ADCINT[8:1] interrupts from the Analog Subsystem. The NMI Watchdog does not send any events to the
µDMA or the NVIC (only to the Resets block).
3.3.3 Cortex-M3 Interrupts
Table 3-15 shows all interrupt assignments for the Cortex-M3 processor. Most interrupts (16–107) are
associated with interrupt requests from Cortex-M3 peripherals. The first 15 interrupts (1–15) are processor
exceptions generated by the Cortex-M3 core itself. These processor exceptions are detailed in Table 3-16.
Table 3-15. Interrupts from NVIC to Cortex-M3
Interrupt Number
Vector Number Vector Address or Offset Description
(Bit in Interrupt Registers)
– 0–15 0x0000.0000–0x0000.003C Processor exceptions
0 16 0x0000.0040 GPIO Port A
1 17 0x0000.0044 GPIO Port B
2 18 0x0000.0048 GPIO Port C
3 19 0x0000.004C GPIO Port D
4 20 0x0000.0050 GPIO Port E
5 21 0x0000.0054 UART0
6 22 0x0000.0058 UART1
7 23 0x0000.005C SSI0
8 24 0x0000.0060 I2C0
9–17 25–33 – Reserved
18 34 0x0000.0088 Watchdog Timers 0 and 1
19 35 0x0000.008C Timer 0A
20 36 0x0000.0090 Timer 0B
21 37 0x0000.0094 Timer 1A
22 38 0x0000.0098 Timer 1B
23 39 0x0000.009C Timer 2A
24 40 0x0000.00A0 Timer 2B
25–27 41–43 – Reserved
28 44 0x0000.00B0 System Control
29 45 – Reserved
30 46 0x0000.00B8 GPIO Port F
31 47 0x0000.00BC GPIO Port G
32 48 0x0000.00C0 GPIO Port H
33 49 0x0000.00C4 UART2
34 50 0x0000.00C8 SSI1
35 51 0x0000.00CC Timer 3A
36 52 0x0000.00D0 Timer 3B
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