Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B

SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014

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7.3.6.1 Functional Overview

The SPI operates in master or slave mode. The master initiates data transfer by sending the SPICLK

signal. For both the slave and the master, data is shifted out of the shift registers on one edge of the

SPICLK and latched into the shift register on the opposite SPICLK clock edge. If the CLOCK PHASE bit

(SPICTL.3) is high, data is transmitted and received a half-cycle before the SPICLK transition. As a result,

both controllers send and receive data simultaneously. The application software determines whether the

data is meaningful or dummy data. There are three possible methods for data transmission:

• Master sends data; slave sends dummy data

• Master sends data; slave sends data

• Master sends dummy data; slave sends data

The master can initiate a data transfer at any time because it controls the SPICLK signal. The software,

however, determines how the master detects when the slave is ready to broadcast data.

7.3.6.2 SPI Electrical Data and Timing

This section contains both Master Mode and Slave Mode timing data.

7.3.6.2.1 Master Mode Timing

Table 7-40 lists the master mode timing (clock phase = 0) and Table 7-41 lists the timing (clock

phase = 1). Figure 7-42 and Figure 7-43 show the timing waveforms.

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