Datasheet

PIN
SPISOMIA
SPISIMOA
PIN
GPIO_MUX1
SPI (C28)
SPIRXINA
INTR
TX FIFO
(1)
RX FIFO
(1)
C28x PIE
C28x
CPU
REGISTER ACCESS
SYSTEM
CONTROL
REGISTERS
C28CLKIN
C28SYSCLK
SPIA_ENCLK
MASTER
SUBSYSTEM
SPI BIT RATE
C28LSPCLK
/1
/2
/4
…
/14
RX INTERRUPT LOGIC
SPITXINA
TX INTERRUPT LOGIC
REGISTER
ACCESS
SPICCR REG
SPICTL REG
SPIST REG
SPIBRR REG
SPIRXEMU REG
SPIRXBUF REG
SPITXBUF REG
SPIDAT REG
SPIFFTX REG
SPIFFRX REG
SPIFFCT REG
SPIPRI REG
PIN
SPICLKA
SPISTEA
PIN
TX DELAY
TX/RX
LOGIC
(1) RX FIFO AND TX FIFO CAN BE BYPASSED BY CONFIGURING BIT SPIFFENA OF THE SPIFFTX REGISTER
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Figure 7-41. SPI (C28x)
Copyright © 2012–2014, Texas Instruments Incorporated Peripheral Information and Timings 227
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