Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B

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SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014

7.3.5.1 Architecture

The major elements used in full-duplex operation include:

• A transmitter (TX) and its major registers:

– SCITXBUF register – Transmitter Data Buffer register. Contains data (loaded by the CPU) to be

transmitted

– TXSHF register – Transmitter Shift register. Accepts data from the SCITXBUF register and shifts

data onto the SCITXD pin, one bit at a time

• A receiver (RX) and its major registers:

– RXSHF register – Receiver Shift register. Shifts data in from the SCIRXD pin, one bit at a time

– SCIRXBUF register – Receiver Data Buffer register. Contains data to be read by the CPU. Data

from a remote processor is loaded into the RXSHF register and then into the SCIRXBUF and

SCIRXEMU registers

• A programmable baud generator

• Data-memory-mapped control and status registers enable the CPU to access the I

C module registers

and FIFOs.

The SCI receiver and transmitter can operate either independently or simultaneously.

7.3.5.2 Multiprocessor and Asynchronous Communication Modes

The SCI has two multiprocessor protocols: the idle-line multiprocessor mode and the address-bit

multiprocessor mode. These protocols allow efficient data transfer between multiple processors.

The SCI offers the UART communications mode for interfacing with many popular peripherals. The

asynchronous mode requires two lines to interface with many standard devices such as terminals and

printers that use RS-232-C formats.

Data transmission characteristics include:

• One start bit

• One to eight data bits

• An even/odd parity bit or no parity bit

• One or two stop bits with a programmed frequency

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