Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
7.3.4.1 Functional Overview
Each device connected to an I
2
C Bus is recognized by a unique address. Each device can operate as
either a transmitter or a receiver, depending on the function of the device. A device connected to the I
2
C
Bus can also be considered as the master or the slave when performing data transfers. A master device is
the device that initiates a data transfer on the bus and generates the clock signals to permit that transfer.
During this transfer, any device addressed by this master is considered a slave. The I
2
C module supports
the multi-master mode, in which one or more devices capable of controlling an I
2
C Bus can be connected
to the same I
2
C Bus.
For data communication, the I
2
C module has a serial data pin (SDA) and a serial clock pin (SCL). These
two pins carry information between the C28x device and other devices connected to the I
2
C Bus. The SDA
and SCL pins both are bidirectional. They each must be connected to a positive supply voltage using a
pullup resistor. When the bus is free, both pins are high. The driver of these two pins has an open-drain
configuration to perform the required wired-AND function. There are two major transfer techniques:
1. Standard Mode: Send exactly n data values, where n is a value you program in an I
2
C module register.
2. Repeat Mode: Keep sending data values until you use software to initiate a STOP condition or a new
START condition.
The I
2
C module consists of the following primary blocks:
• A serial interface: one data pin (SDA) and one clock pin (SCL)
• Data registers and FIFOs to temporarily hold receive data and transmit data traveling between the
SDA pin and the CPU
• Control and status registers
• A peripheral bus interface to enable the CPU to access the I
2
C module registers and FIFOs.
7.3.4.2 Clock Generation
The device clock generator receives a signal from an external clock source and produces an I
2
C input
clock with a programmed frequency. The I
2
C input clock is equivalent to the CPU clock and is then divided
twice more inside the I
2
C module to produce the module clock and the master clock.
7.3.4.3 I
2
C Electrical Data and Timing
Table 7-39. I
2
C Timing
TEST CONDITIONS MIN MAX UNIT
f
SCL
SCL clock frequency I
2
C clock module frequency is between 400 kHz
7 MHz and 12 MHz and I
2
C prescaler and
clock divider registers are configured
appropriately
v
il
Low level input voltage 0.3 V
DDIO
V
V
ih
High level input voltage 0.7 V
DDIO
V
V
hys
Input hysteresis 0.05 V
DDIO
V
V
ol
Low level output voltage 3 mA sink current 0 0.4 V
t
LOW
Low period of SCL clock I
2
C clock module frequency is between 1.3 μs
7 MHz and 12 MHz and I
2
C prescaler and
clock divider registers are configured
appropriately
t
HIGH
High period of SCL clock I
2
C clock module frequency is between 0.6 μs
7 MHz and 12 MHz and I
2
C prescaler and
clock divider registers are configured
appropriately
l
I
Input current with an input voltage –10 10 μA
between 0.1 V
DDIO
and 0.9 V
DDIO
MAX
222 Peripheral Information and Timings Copyright © 2012–2014, Texas Instruments Incorporated
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