Datasheet

PIN
I2CASDA
I2CASCL
PIN
GPIO_MUX1
I C (C28)
2
I2CINT1A
INTR
TX FIFO
RX FIFO
I2CXSR REG
I2CDRR REG
I2CRXR REG
I2CDXR REG
I2CIER REG
C28x PIE
I2CINT2A
C28x
CPU
REGISTER
ACCESS
SYSTEM
CONTROL
REGISTERS
C28CLKIN
C28SYSCLK
I2CA_ENCLK
MASTER
SUBSYSTEM
SLAVE CLOCK
SYNCHRONIZER
INTERRUPT
CONTROL AND
ARBITRATION
CLOCK
PRESCALER
I2CCLK
I2COAR REG
I2CCLKL REG
I2CCLKH REG
I2CCNT REG
I2CSAR REG
I2CMDR REG
I2CISRC REG
I2CPSC REG
I2CFFTX REG
I2CFFRX REG
MASTER CLOCK
DIVIDER
MODE AND STATUS
REGISTERS
I2CSTR REG
I2CCLK
REGISTER
ACCESS CLK
TX/RX
LOGIC
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Figure 7-39. I
2
C (C28x)
Copyright © 2012–2014, Texas Instruments Incorporated Peripheral Information and Timings 221
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