Datasheet
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
www.ti.com
7.3.4 C28x Inter-Integrated Circuit Module
This device has one C28x I
2
C peripheral. The I
2
C provides an interface between a Concerto device and
devices compliant with the Philips
®
I
2
C-Bus Specification Version 2.1 and connected by way of an I
2
C bus.
External components attached to this 2-wire serial bus can transmit 1-bit to 8-bit data to and receive 1-bit
to 8-bit data from the device through the I
2
C module.
NOTE
A unit of data transmitted or received by the I
2
C module can have fewer than 8 bits;
however, for convenience, a unit of data is called a data byte in this section. The number of
bits in a data byte is selectable via the BC bits of the mode register, I2CMDR.
The I
2
C module has the following features:
• Compliance with the Philips I
2
C-Bus Specification Version 2.1:
– Support for 1-bit to 8-bit format transfers
– 7-bit and 10-bit addressing modes
– General call
– START byte mode
– Support for multiple master-transmitters and slave-receivers
– Support for multiple slave-transmitters and master-receivers
– Combined master transmit-and-receive and receive-and-transmit mode
– Data transfer rate of from 10 Kbps up to 400 Kbps (I
2
C Fast-mode rate)
• One 4-word receive FIFO and one 4-word transmit FIFO
• One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the
following conditions:
– Transmit-data ready
– Receive-data ready
– Register-access ready
– No-acknowledgment received
– Arbitration lost
– Stop condition detected
– Addressed as slave
• An additional interrupt that can be used by the CPU when in FIFO mode
• Module enable or disable capability
• Free data format mode
The I
2
C module does not support:
• High-speed mode (Hs-mode)
• CBUS-compatibility mode
Figure 7-39 shows the C28x I
2
C peripheral.
220 Peripheral Information and Timings Copyright © 2012–2014, Texas Instruments Incorporated
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