Datasheet

BUS
MATRIX
EPI
I C (2)
2
SSI (4)
UART (5)
USB + PHY
(OTG)
EMAC
CAN (2)
GP TIMER (4)
uCRC
WDOG (2)
NMI WDOG
M3 NMI
NVIC
(NESTED VECTORED INTERRUPT CONTROLLER)
BOOT
ROM
uDMA
RESETS
MPU /
BRIDGE
SECURE
FLASH
(ECC)
FLASHUNCERR
BUSFAULT
BUS CNTRL/FAULT LOGIC
LOCAL MEMORY
MEMORY MNGMT
FLFSMFLSINGER
ANALOG SUBSYSTEM
EXCEPTIONS
FROM M3 CORE
M3NMIINT
M3PORRST
M3HRDFLT
INSTRUCTIONS
D-CODE BUS
M3 SYSTEM BUS
AHB BUS
APB BUS
I-CODE BUS
M3
CPU
M3SYSRST
UART
(5:1)
REQ
SSI
(3:0)
REQ
USB
MAC
REQ
EPI
REQ
GPTA/B
(3:0)
(3:0)
REQ
EMACRX
EMACTX
REQ
M3DBGRST
M3WDRST
(1:0)
M3NMIRST
M3SWRST
M3NMI
USAGE FAULT
SVCALL
DBG MONITOR
PENDING SV
SYS TICK
PROGRAM-
MABLE
PRIORITY
INTERRUPTS
FIXED
PRIORITY
INTERRUPTS
GPIO_MUX1
DMA INTRS
DATA
INTERRUPTS
1
2
3
APB BUS (REG ACCESS ONLY)
NVIC
M3NMIINT
ADC
INT
(8:1)
M3NMIINT
EOC INTERRUPTS
M3 PERIPHERALS
UART
(1:5)
IRQ
SSI
(0:3)
IRQ
I2C
(1:0)
IRQ
CAN0/1
(1:0)
(1:0)
IRQ
USB
MAC
IRQ
EPI
IRQ
GPTA/B
(3:0)
(3:0)
IRQ
GPIO
(S:A)
IRQ
WDT
(1:0)
IRQ
EMAC
IRQ
DMA
SW
IRQ
DMA
ERR
IRQ
PERIPHERAL
I/O s
RAMUNCERR
S0-S7
SHARED
RAM
(parity)
MTOC
MSG
RAM
(parity)
CTOM
MSG
RAM
(parity)
SHARED RESOURCES
CONTROL SUBSYSTEM
uDMA BUS
CTOM IPC (4:1)
IPC
REGS
FREQ
GASKET
BUS
BRIDGE
C2 - C15
RAM
(parity)
SECURE
C0/C1
RAM
(ECC)
RAMUNCERRRAMACCVIOL
RAMSINGERR
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
Figure 3-1. Master Subsystem
22 Device Overview Copyright © 2012–2014, Texas Instruments Incorporated
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Product Folder Links: F28M36P63C F28M36P53C F28M36H53C F28M36H53B F28M36H33C F28M36H33B