Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
7.3 Control Subsystem Peripherals
Control Subsystem peripherals are accessible from the C28x CPU via the C28x Memory Bus, and from
the C28x DMA via the C28x DMA Bus. They include one NMI Watchdog, three Timers, four Serial Port
Peripherals (SCI, SPI, McBSP, I
2
C), and three types of Control Peripherals (ePWM, eQEP, eCAP).
Additionally, the C28x CPU/DMA also have access to the EPI, and to Analog and Shared peripherals (see
Section 7.1).
For detailed information on the processor peripherals, see the Concerto F28M36x Technical Reference
Manual (literature number SPRUHE8).
7.3.1 High-Resolution PWM and Enhanced PWM Modules
There are 12 PWM modules in the Concerto device. Eight of these are of the HRPWM type with high-
resolution control on both A and B signal outputs, and four are of the ePWM type. The HRPWM modules
have all the features of the ePWM plus they offer significantly higher PWM resolution (time granularity on
the order of 150 ps). Figure 7-34 shows the eight HRPWM modules (PWM 1–8) and four ePWM modules
(PWM 9–PWM12).
The synchronization inputs to the PWM modules include the SYNCI signal from the GPTRIP1 output of
GPIO_MUX1, and the TBCLKSYNC signal from the CPCLKCR0 register. Synchronization output
SYNCO1 comes from the ePWM1 module and is stretched by 8 HSPCLK cycles before entering
GPIO_MUX1. There are two groups of trip signal inputs to PWM modules. TRIP1–15 inputs come from
GPTRIP1–12 (from GPIO_MUX1), ECCDBLERR signal (from C28x Local and Shared RAM), and PIEERR
signal from the C28x CPU. TZ1–6 (Trip Zone) inputs come from GPTRIP 1–3 (from GPIO_MUX1),
EQEPERR (from the eQEP peripheral), CLOCKFAIL (from M3 CLOCKS), and EMUSTOP (from the C28x
CPU).
There are 12 SOCA PWM outputs and 12 SOCB PWM outputs—a pair from each PWM module. The
12 SOCA outputs are OR-ed together and stretched by 32 HSPCLK cycles before entering GPIO_MUX1
as a single SOCAO signal. The 12 SOCB outputs are OR-ed together and stretched by 32 HSPCLK
cycles before entering GPIO_MUX1 as a single SOCBO signal. The 18 SOCA/B outputs from
PWM1–PWM9 also go to the Analog Subsystem, where they can be selected to become conversion
triggers to ADC modules.
The 12 PWM modules also drive two other sets of outputs which can interrupt the C28x CPU via the C28x
PIE block. These are 12 EPWMINT interrupts and 12 EPWMTZINT trip-zone interrupts. See Figure 7-35
for the internal structure of the HRPWM and ePWM modules. The green-colored blocks are common to
both ePWM and HRPWM modules, but only the HRPWMs have the grey-colored hi-resolution blocks.
Copyright © 2012–2014, Texas Instruments Incorporated Peripheral Information and Timings 211
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