Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
7.2.6 Cortex-M3 Ethernet Media Access Controller
The Cortex-M3 EMAC conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-
TX standards. This device has one Ethernet Media Access Controller.
The EMAC module has the following features:
• Conforms to the IEEE 802.3-2002 specification
– 10BASE-T/100BASE-TX IEEE-802.3 compliant
• Multiple operational modes
– Full- and half-duplex 100-Mbps
– Full- and half-duplex 10-Mbps
– Power-saving and power-down modes
• Highly configurable:
– Programmable MAC address
– Promiscuous mode support
– CRC error-rejection control
– User-configurable interrupts
• IEEE 1588 Precision Time Protocol: Provides highly accurate time stamps for individual packets
• Efficient transfers using the Micro Direct Memory Access Controller (µDMA)
– Separate channels for transmit and receive
– Receive channel request asserted on packet receipt
– Transmit channel request asserted on empty transmit FIFO
Figure 7-26 shows the EMAC peripheral.
7.2.6.1 Functional Overview
The Ethernet Controller is functionally divided into two layers: the Media Access Controller (MAC) layer
and the Network Physical (PHY) layer. The MAC resides inside the device, and the PHY outside of the
device. These layers correspond to the OSI model layers 2 and 1, respectively. The CPU accesses the
Ethernet Controller via the MAC layer. The MAC layer provides transmit and receive processing for
Ethernet frames. The MAC layer also provides the interface to the external PHY layer via an internal
Media Independent Interface (MII). The PHY layer communicates with the Ethernet bus.
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