Datasheet

M3
CPU
REGISTER
ACCESS
M3SSCLK USBCLKENB
M3 CLOCKS
M3 NVIC
USBMAC_IRQ
INTR
USB
M3
uDMA
DMAxREQ
TX/RX FIFO
ACCESS
USBMAC REQ
PIN
USB0DM
PIN
PIN
PIN
GPIO_MUX1
PACKET ENCODE
PACKET DECODE
CRC GEN/CHECK
PACKET
ENCODE / DECODE
CYCLE CONTROL
RX
BUFF
RX
BUFF
TX
BUFF
TX
BUFF
FIFO RAM CONTROLLER
TRANSMIT
RECEIVE
EP 0-31
CONTROL
COMBINE
ENDPOINTS
HOST TRANSACTION
SCHEDULER
ENDPOINT CONTROLCPU
INTERFACE
INTERRUPT
CONTROL
EP REGISTER
DECODER
COMMON
REGS
CYCLE
CONTROL
FIFO DECODER
DATA SYNC
HNP / SRP
TIMERS
UTM
SYNCHRONIZATION
PIN
PIN
USB0DP
USB0VBUS
USB0ID
USB0EPEN
USB0PFLT
PHY
USBPLLCLK
(5V TOLERANT)
(5V TOLERANT)
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
Figure 7-25. USB
204 Peripheral Information and Timings Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: F28M36P63C F28M36P53C F28M36H53C F28M36H53B F28M36H33C F28M36H33B