Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B

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SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014

7.2.2.4 Interrupts

The UART can generate interrupts when the following conditions are observed:

• Overrun Error

• Break Error

• Parity Error

• Framing Error

• Receive Time-out

• Transmit (when the condition defined in the TXIFLSEL bit in the UARTIFLS register is met, or if the

EOT bit in UARTCTL is set, when the last bit of all transmitted data leaves the serializer)

• Receive (when the condition defined in the RXIFLSEL bit in the UARTIFLS register is met)

All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can

only generate a single interrupt request to the controller at any given time. Software can service multiple

interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status

(UARTMIS) register.

The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask

(UARTIM) register by setting the corresponding IM bits. If interrupts are not used, the raw interrupt status

is always visible via the UART Raw Interrupt Status (UARTRIS) register.

Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by writing a "1" to the

corresponding bit in the UART Interrupt Clear (UARTICR) register.

The receive time-out interrupt is asserted when the receive FIFO is not empty, and no further data is

received over a 32-bit period. The receive time-out interrupt is cleared either when the FIFO becomes

empty through reading all the data (or by reading the holding register), or when a "1" is written to the

corresponding bit in the UARTICR register.

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