Datasheet

TX FIFO
( 8 x 16 )
TRANSMITTER
UxRX
UxTX
PIN
PIN
GPIO_MUX1
RX FIFO
( 8 x 16 )
CONTROL
/ STATUS
UARTDR REG
INTR CONTROL
UARTCR0 REG
UARTCR1 REG
UARTSR REG
UARTRIS REG
UARTICR REG
UARTIM REG
UARTPERIPHLD4
M3
CPU
REGISTER
ACCESS
M3SSCLK
UART
UARTCLKENBx
M3 CLOCKS
M3 NVIC
UARTxIRQ
UARTPERIPHLD5
UARTPERIPHLD6
UARTPCELLID0
UARTPCELLID1
UARTPCELLID2
UARTPCELLID3
UARTPERIPHLD0
UARTPERIPHLD1
UARTPERIPHLD2
UARTPERIPHLD3 UARTPERIPHLD7
UARTMIS REG
UARTDMACTL REG
DMA
CONTROL
UARTIBRD REG
BAUDE RATE
GENERATOR
INTxREQ
TX
FIFO
STAT
RX
FIFO
STAT
IDENTIFICATION REGISTERS
INTR
UARTIFLS REG
UARTFBRD REG
XCLK
UARTxCLK
M3
uDMA
DMAxREQ
TX/RX FIFO
ACCESS
RECEIVER
(WITH SIR RECEIVE
DECODER)
(WITH SIR TRANSMIT
ENCODER)
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Figure 7-22. UART
Copyright © 2012–2014, Texas Instruments Incorporated Peripheral Information and Timings 195
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