Datasheet

TRANSMIT
/ RECEIVE
LOGIC
PIN
SSIFSS
SSICLK
SSIRX
SSITX
PIN
PIN
PIN
GPIO_MUX1
CONTROL
/ STATUS
INTR CONTROL
SSICR0 REG
SSICR1 REG
SSISR REG
SSIRIS REG
SSIICR REG
SSIIM REG SSIPERIPHLD4 REG
M3
CPU
REGISTER
ACCESS
M3SSCLK
SSI
M3CLKENBx
M3 CLOCKS
M3
uDMA
M3 NVIC
SSIxIRQ
SSIPERIPHLD5 REG
SSIPERIPHLD6 REG
SSIPCELLID0 REG
SSIPCELLID1 REG
SSIPCELLID2 REG
SSIPCELLID3 REG
SSIPERIPHLD0 REG
SSIPERIPHLD1REG
SSIPERIPHLD2 REG
SSIPERIPHLD3 REG SSIPERIPHLD7 REG
SSIMIS REG
SSIDMACTL REG
DMA
CONTROL
SSICPSR REG
CLOCK
PRESCALER
SSIxCLK
INTxREQ
DMAxREQ
TX
FIFO
STAT
RX
FIFO
STAT
IDENTIFICATION REGISTERS
INTR
TX/RX FIFO
ACCESS
TX FIFO
( 8 x 16 )
RX FIFO
( 8 x 16 )
SSIDR REG
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Figure 7-21. SSI
Copyright © 2012–2014, Texas Instruments Incorporated Peripheral Information and Timings 191
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