Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
7.2 Master Subsystem Peripherals
Master Subsystem peripherals are located on the APB Bus and AHB Bus, and are accessible from the
Cortex-M3 CPU/µDMA. The AHB peripherals include EPI, USB, and two CAN modules. The APB
peripherals include EMAC, two I
2
Cs, five UARTs, four SSIs, four GPTIMERs, two WDOGs, NMI WDOG,
and a µCRC module (Cyclic Redundancy Check). The Cortex-M3 CPU/µDMA also have access to Analog
(Result Registers only) and Shared peripherals (see Section 7.1).
For detailed information on the processor peripherals, see the Concerto F28M36x Technical Reference
Manual (literature number SPRUHE8).
7.2.1 Synchronous Serial Interface
This device has four SSI modules. Each SSI has a Master or Slave interface for synchronous serial
communication with peripheral devices that have Texas Instruments™ SSIs, SPI, MICROWIRE, or
Freescale™ serial format.
The SSI peripheral performs serial-to-parallel conversion on data received from a peripheral device. The
CPU accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories, allowing up to eight 16-bit values to be stored independently in both transmit and
receive modes. The SSI also supports µDMA transfers. The transmit and receive FIFOs can be
programmed as destination/source addresses in the µDMA module. An µDMA operation is enabled by
setting the appropriate bit or bits in the SSIDMACTL register.
Figure 7-21 shows the SSI peripheral.
7.2.1.1 Bit Rate Generation
The SSI includes a programmable bit-rate clock divider and prescaler to generate the serial output clock.
Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral
devices. The serial bit rate is derived by dividing-down the input clock (SysClk). The clock is first divided
by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register. The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR
is the value programmed in the SSI Control 0 (SSICR0) register. The frequency of the output clock SSIClk
is defined by:
SSIClk = SysClk / [CPSDVSR * (1 + SCR)]
NOTE
For master mode, the system clock must be at least four times faster than SSIClk, with the
restriction that SSIClk cannot be faster than 25 MHz. For slave mode, the system clock must
be at least 12 times faster than SSIClk.
190 Peripheral Information and Timings Copyright © 2012–2014, Texas Instruments Incorporated
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