Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Table 3-12. Master Subsystem Peripherals (continued)
µDMA M Address Master Subsystem Size C Address
C DMA Access
(2)
Access (Byte-Aligned)
(1)
Peripherals (Bytes) (x16 Aligned)
(2)
yes 4005 F000 – 4005 FFFF M GPIO Port H (AHB Bus)
(1)
4K
yes 4006 0000 – 4006 0FFF M GPIO Port J (AHB Bus)
(1)
4K
yes 4006 1000 – 4006 1FFF M GPIO Port K (AHB Bus)
(1)
4K
yes 4006 2000 – 4006 2FFF M GPIO Port L (AHB Bus)
(1)
4K
yes 4006 3000 – 4006 3FFF M GPIO Port M (AHB Bus)
(1)
4K
yes 4006 4000 – 4006 4FFF M GPIO Port N (AHB Bus)
(1)
4K
yes 4006 5000 – 4006 5FFF M GPIO Port P (AHB Bus)
(1)
4K
yes 4006 6000 – 4006 6FFF M GPIO Port Q (AHB Bus)
(1)
4K
yes 4006 7000 – 4006 7FFF M GPIO Port R (AHB Bus)
(1)
4K
yes 4006 8000 – 4006 8FFF M GPIO Port S (AHB Bus)
(1)
4K
4006 9000 – 4006 FFFF Reserved
no 4007 0000 – 4007 3FFF CAN0 16K
no 4007 4000 – 4007 7FFF CAN1 16K
4007 8000 – 400C FFFF Reserved
no 400D 0000 – 400D 0FFF EPI0 (Registers only) 4K
400D 1000 – 400F 9FFF Reserved
no 400F A000 – 400F A303 M Flash Control Registers
(3)
772
400F A304 – 400F A5FF Reserved
M Flash ECC Error Log
no 400F A600 – 400F A647 72
Registers
(3)
400F A648 – 400F AFFF Reserved
no 400F B000 – 400F B1FF PBIST Control Registers 512
no 400F B200 – 400F B2FF RAM Configuration Registers 256 0000 4900 – 0000 497F no
RAM ECC/Parity/Access Error
no 400F B300 – 400F B3FF 256 0000 4A00 – 0000 4A7F no
Log Registers
no 400F B400 – 400F B5FF M CSM Registers
(1)
512
no 400F B600 – 400F B67F µCRC 128
400F B680 – 400F B6FF Reserved
no 400F B700 – 400F B77F CtoM and MtoC IPC Registers 128 0000 4E00 – 0000 4E3F no
400F B780 – 400F B7FF Reserved
no 400F B800 – 400F B87F M Clock Control Registers
(1)
128 0000 4400 – 0000 443F no
no 400F B880 – 400F B8BF M LPM Control Registers
(1)
64
no 400F B8C0 – 400F B8FF M Reset Control Registers
(1)
64
0000 0880 – 0000 0890
no 400F B900 – 400F B93F Device Configuration Registers 64
(Read Only)
400F B940 – 400F B97F Reserved
no 400F B980 – 400F B9FF M Write Protect Registers
(1)
128
no 400F BA00 – 400F BA7F M NMI Registers
(1)
128
400F BA80 – 400F BAFF Reserved
no 400F BB00 – 400F BBFF M HWBIST Registers 256
400F BC00 – 400F EFFF Reserved
no 400F F000 – 400F FFFF µDMA Registers 4K
4010 0000 – 41FF FFFF Reserved
Bit Banded Peripheral Zone
(Dedicated address for each
yes 4200 0000 – 43FF FFFF 32M
register bit of Cortex-M3
peripherals above.)
4400 0000 – 4FFF FFFF Reserved
(3) The letter "M" refers to the Master Subsystem.
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