Datasheet

Clock
( )EPI0S31
Frame
(EPI0S30)
RD
( )EPI0S29
iRDY
( )EPI0S27
Address
Data
E32 E32
Read
Data
E28
E31
Data
E33
E27
E26
E30
Clock
( )EPI0S31
Frame
(EPI0S30)
RD
( )EPI0S29
WR
( )EPI0S28
Address
Data
E29
E30
Write
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Table 7-20. EPI General-Purpose Interface Switching Characteristics Over Recommended Operating
Conditions (Unless Otherwise Noted) (see Figure 7-19)
NO. PARAMETER MIN MAX UNIT
E26 t
w(CKH)
Pulse duration, general-purpose clock high 10 ns
E27 t
w(CKL)
Pulse duration, general-purpose clock low 10 ns
E30 t
d(CK-OV)
Delay time, falling clock edge to output valid –5 5 ns
E31 t
d(CK-OIV)
Delay time, falling clock edge to output invalid –5 5 ns
E33 t
c(CK)
Cycle time, general-purpose clock 20 ns
Table 7-21. EPI General-Purpose Interface Timing Requirements (see Figure 7-19 and Figure 7-20)
NO. MIN MAX UNIT
E28 t
su(IN-CK)
Setup time, input signal before rising clock edge 10 ns
E29 t
h(CK-IN)
Hold time, input signal after rising clock edge 0 ns
E32 t
su(IRDY-CK)
Setup time, iRDY assertion or de-assertion before falling clock edge 10 ns
A. This figure illustrates accesses where the FRM50 bit is clear, the FRMCNT field is 0x0, the RD2CYC bit is clear, and
the WR2CYC bit is clear.
Figure 7-19. General-Purpose Mode Read and Write Timing
Figure 7-20. General-Purpose Mode iRDY Timing
Copyright © 2012–2014, Texas Instruments Incorporated Peripheral Information and Timings 189
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