Datasheet

Data
ALE
( )EPI0S30
CS
(EPI0S30)
WR
( )EPI0S29
RDOE/
( )EPI0S28
Address
Data
E15
E18
E18
E14
E19
E20
E24
E22
E23
BSEL0BSEL1/
(A)
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Table 7-18. EPI Host-Bus 8 and Host-Bus 16 Interface Switching Characteristics Over Recommended
Operating Conditions (Unless Otherwise Noted)
(see Figure 7-15, Figure 7-16, Figure 7-17, and Figure 7-18)
NO. PARAMETER MIN TYP MAX UNIT
E16 t
d(WR-WDATAV)
Delay time, WR to write data valid 5 ns
EPI
E17 t
d(WRIV-DATA)
Delay time, WR invalid to data 2
clocks
E18 t
d(CS-OV)
Delay time, CS to output valid –5 5 ns
E19 t
d(CS-OIV)
Delay time, CS to output invalid –5 5 ns
EPI
E20 t
w(STL)
Pulse duration, WR/RD strobe low 2
clocks
EPI
E22 t
w(ALEH)
Pulse duration, ALE high 1
clocks
EPI
E23 t
w(CSL)
Pulse duration, CS low 4
clocks
EPI
E24 t
d(ALE-ST)
Delay time, ALE rising to WR/RD strobe falling 2
clocks
EPI
E25 t
d(ALE-ADHZ)
Delay time, ALE falling to Address/Data high-impedance 1
clocks
Table 7-19. EPI Host-Bus 8 and Host-Bus 16 Interface Timing Requirements
(1)
(see Figure 7-15 and Figure 7-17)
NO. MIN MAX UNIT
E14 t
su(RDATA)
Setup time, read data 10 ns
E15 t
h(RDATA)
Hold time, read data 0 ns
(1) Setup time for FEMPTY and FFULL signals from clock edge is 2 system clocks (MIN).
A. BSEL0 and BSEL1 are available in Host-Bus 16 mode only.
Figure 7-15. Host-Bus 8/16 Mode Read Timing
Copyright © 2012–2014, Texas Instruments Incorporated Peripheral Information and Timings 187
Submit Documentation Feedback
Product Folder Links: F28M36P63C F28M36P53C F28M36H53C F28M36H53B F28M36H33C F28M36H33B