Datasheet

Row Column Data 0 Data 1 ... Data n
CLK
(EPI0S31)
CKE
(EPI0S30)
CS
(EPI0S29)
WE
(EPI0S28)
RAS
(EPI0S19)
CAS
(EPI0S18)
DQMH, DQML
(EPI0S [17:16])
AD [15:0]
(EPI0S [15:0])
Activate NOP NOP Read
NOP
Burst
Term
AD [15:0] driven in
AD [15:0] driven out AD [15:0] driven out
E4
E5
E6
E7
E8
CLK
(EPI0S31)
CKE
(EPI0S30)
Command
(EPI0S[29:28,19:18])
DQMH, DQML
(EPI0S[17:16])
AD11, AD[9:0]
(EPI0S[11,9:0]
AD10
(EPI0S[10])
BAD[1:0]
(EPI0S[14:13])
AD [15,12]
(EPI0S [15,12])
NOP
PRE
NOP
AREF
NOP
PRE
NOP
AREF
NOP
LOAD
Code
All Banks
Single Bank
Code
E9
E10 E11
E12
E1 E2
E3
NOP
AREF
NOP
Active
Row
Row
Bank
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Table 7-17. EPI SDRAM Interface Switching Characteristics Over Recommended Operating Conditions
(Unless Otherwise Noted) (see Figure 7-12, Figure 7-13, and Figure 7-14)
NO. PARAMETER MIN MAX UNIT
E1 t
c(CK)
Cycle time, SDRAM clock 20 ns
E2 t
w(CKH)
Pulse duration, SDRAM clock high 10 ns
E3 t
w(CKL)
Pulse duration, SDRAM clock low 10 ns
E4 t
d(CK-OV)
Delay time, clock to output valid –5 5 ns
E5 t
d(CK-OIV)
Delay time, clock to output invalid –5 5 ns
E6 t
d(CK-OZ)
Delay time, clock to output high-impedance –5 5 ns
E7 t
su(AD-CK)
Setup time, input before clock 10 ns
E8 t
h(CK-AD)
Hold time, input after clock 0 ns
E9 t
PU
Power-up time 100 µs
E10 t
pc
Precharge time, all banks 20 ns
E11 t
rf
Autorefresh 66 ns
E12 t
MRD
Program mode register 40 ns
A. If CS is high at clock high time, all applied commands are NOP.
B. The Mode register may be loaded prior to the autorefresh cycles if desired.
C. JEDEC and PC100 specify three clocks.
D. Outputs are ensured High-Z after command is issued.
Figure 7-12. SDRAM Initialization and Load Mode Register Timing
Figure 7-13. SDRAM Read Timing
Copyright © 2012–2014, Texas Instruments Incorporated Peripheral Information and Timings 185
Submit Documentation Feedback
Product Folder Links: F28M36P63C F28M36P53C F28M36H53C F28M36H53B F28M36H33C F28M36H33B