Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
Table 7-15. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
FIFO Mode (EPIHB16CFG/MODE = 0x3) (continued)
EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN
With One With Two
Accessible by (Available GPIOMUX_1
Accessible by C28x Chip Select Chip Selects
Cortex-M3 Muxing Choices for EPI)
(CSCFG = 0x1) (CSCFG = 0x2)
EPI0S33 x x PF3_GPIO35 PC1_GPIO65
EPI0S34 x x PE4_GPIO28
EPI0S35 x x PE5_GPIO29
EPI0S36 x x PB7_GPIO15 PC3_GPIO67
EPI0S37 x x PB6_GPIO14 PC2_GPIO66
EPI0S38 x x PF6_GPIO38 PE4_GPIO28
EPI0S39 x x PG2_GPIO42
EPI0S40 x x PG5_GPIO45
EPI0S41 x x PG6_GPIO46
EPI0S42 x x PN6_GPIO102
EPI0S43 x x PN7_GPIO103
7.1.4.4 EPI Electrical Data and Timing
The signal names in Figure 7-12 through Figure 7-20 are defined in Table 7-16.
Table 7-16. Signals in Figure 7-12 Through Figure 7-20
SIGNAL DESCRIPTION
AD Address/Data
Address Address output
ALE Address latch enable
BAD Bank Address/Data
BSEL0, BSEL1 Byte select
CAS Column address strobe
CKE Clock enable
CLK, Clock Clock
Command Command signal
CS Chip select
Data Data signals
DQMH Data mask high
DQML Data mask low
Frame Frame signal
iRDY Ready input
Muxed Address/Data Multiplexed Address/Data
RAS Row address strobe
RD/OE Read enable/Output enable
WE, WR Write enable
184 Peripheral Information and Timings Copyright © 2012–2014, Texas Instruments Incorporated
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