Datasheet
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
www.ti.com
Table 7-10. EPI MODES – 16-Bit Host-Bus (EPICFG/MODE = 0x3),
Muxed (EPIHB16CFG/MODE = 0x0), With Byte Selects (EPIHB16CFG/BSEL = 0x0),
and With Chip Selects (EPIHB16CFG2/CSCFG=0x0,1,2,3) (continued)
EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN
With With With With
Accessible by Accessible by Address Latch One Two ALE and Two (Available GPIOMUX_1
Cortex-M3 C28x Enable Chip Select Chip Selects Chip Selects Muxing Choices for EPI)
(CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3)
EPI0S24 A24 A24 A24 BSEL0 PE2_GPIO26
EPI0S25 A25 A25 BSEL0 BSEL1 PE3_GPIO27
EPI0S26 BSEL0 BSEL0 BSEL1 CS0 PH6_GPIO54
EPI0S27 BSEL1 BSEL1 CS1 CS1 PH7_GPIO55
EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62
EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61
EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60
EPI0S31 x x x x PG7_GPIO47
EPI0S32 x x x x PF2_GPIO34 PC0_GPIO64
EPI0S33 x x x x PF3_GPIO35 PC1_GPIO65
EPI0S34 x x x x PE4_GPIO28
EPI0S35 x x x x PE5_GPIO29
EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67
EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66
EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28
EPI0S39 x x x x PG2_GPIO42
EPI0S40 x x x x PG5_GPIO45
EPI0S41 x x x x PG6_GPIO46
EPI0S42 x x x x PN6_GPIO102
EPI0S43 x x x x PN7_GPIO103
7.1.4.3.2.2 HB-16 Non-Muxed Address/Data Mode
The HB-16 Non-Muxed Mode uses dedicated pins for address and data signals. For this reason, the Non-
Muxed Mode has reduced address reach as compared to the Muxed Mode. The HB-16 Non-Muxed Mode
is selected with the MODE field of the HB-16 Configuration Register. In addition to data and address
signals, the HB-16 Non-Muxed Mode also features the ALE signal (indicating to an external latch to
capture address and hold the address until the data phase); RD and WR data strobes; 1–4 CS (chip
select) signals to enable one of four external peripherals; and two BSEL (byte select) signals to
accommodate byte accesses to lower or upper half of 16-bit data. The Byte Selects are chosen with the
BSEL field of the HB-16 Configuration Register. The ALE and CS options are chosen with the CSCFG
field of the HB-16 Configuration2 Register. For Non-Muxed bus cycles, most of the CSCFG modes also
support a RDY signal. The RDY input to EPI is used by an external peripheral to extend bus cycles when
the peripheral needs more time to complete reading or writing of data. While most EPI modes use up to
32 pins, the Non-Muxed CSCFG modes with 3 and 4 Chip Selects use 12 additional pins to extend the
address reach and the number of CS signals. For detailed maps of HB-16 Non-Muxed Modes without
Byte Selects, see Table 7-11 and Table 7-12. For detailed maps of HB-16 Non-Muxed Modes with Byte
Selects, see Table 7-13 and Table 7-14.
178 Peripheral Information and Timings Copyright © 2012–2014, Texas Instruments Incorporated
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