Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
7.1.4.3.2.1 HB-16 Muxed Address/Data Mode
The HB-16 Muxed Mode multiplexes address signals with low-order data signals. For this reason, the
Muxed Mode allows for a larger address space as compared to the Non-Muxed Mode. The HB-16 Muxed
Mode is selected with the MODE field of the HB-16 Configuration Register. In addition to data and address
signals, the HB-16 Muxed Mode also features the ALE signal (indicating to an external latch to capture
address and hold the address until the data phase); RD and WR data strobes; 1–4 CS (chip select)
signals to enable one of four external peripherals; and two BSEL (byte select) signals to accommodate
byte accesses to lower or upper half of 16-bit data. The Byte Selects are chosen with the BSEL field of the
HB-16 Configuration Register. The ALE and CS options are chosen with the CSCFG field of the HB-16
Configuration2 Register. For more detailed maps of the HB-16 Muxed Mode without Byte Selects, see
Table 7-9. For more detailed maps of the HB-16 Muxed Mode with Byte Selects, see Table 7-10.
Table 7-9. EPI MODES – 16-Bit Host-Bus Mode (EPICFG/MODE = 0x3),
Muxed (EPIHB16CFG/MODE = 0x0), Without Byte Selects (EPIHB16CFG/BSEL = 0x1),
and With Chip Selects (EPIHB16CFG2/CSCFG = 0x0,1,2,3)
EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN
With With With With
Accessible by Accessible by Address Latch One Two ALE and Two (Available GPIOMUX_1
Cortex-M3 C28x Enable Chip Select Chip Selects Chip Selects Muxing Choices for EPI)
(CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3)
EPI0S0 AD0 AD0 AD0 AD0 PH3_GPIO51
EPI0S1 AD1 AD1 AD1 AD1 PH2_GPIO50
EPI0S2 AD2 AD2 AD2 AD2 PC4_GPIO68
EPI0S3 AD3 AD3 AD3 AD3 PC5_GPIO69
EPI0S4 AD4 AD4 AD4 AD4 PC6_GPIO70
EPI0S5 AD5 AD5 AD5 AD5 PC7_GPIO71
EPI0S6 AD6 AD6 AD6 AD6 PH0_GPIO48
EPI0S7 AD7 AD7 AD7 AD7 PH1_GPIO49
EPI0S8 AD8 AD8 AD8 AD8 PE0_GPIO24
EPI0S9 AD9 AD9 AD9 AD9 PE1_GPIO25
EPI0S10 AD10 AD10 AD10 AD10 PH4_GPIO52
EPI0S11 AD11 AD11 AD11 AD11 PH5_GPIO53
EPI0S12 AD12 AD12 AD12 AD12 PF4_GPIO36
EPI0S13 AD13 AD13 AD13 AD13 PG0_GPIO40
EPI0S14 AD14 AD14 AD14 AD14 PG1_GPIO41
EPI0S15 AD15 AD15 AD15 AD15 PF5_GPIO37
EPI0S16 A16 A16 A16 A16 PJ0_GPIO56
EPI0S17 A17 A17 A17 A17 PJ1_GPIO57
EPI0S18 A18 A18 A18 A18 PJ2_GPIO58
EPI0S19 A19 A19 A19 A19 PD4_GPIO20 PJ3_GPIO59
EPI0S20 A20 A20 A20 A20 PD2_GPIO18
EPI0S21 A21 A21 A21 A21 PD3_GPIO19
EPI0S22 A22 A22 A22 A22 PB5_GPIO13
EPI0S23 A23 A23 A23 A23 PB4_GPIO12
EPI0S24 A24 A24 A24 A24 PE2_GPIO26
EPI0S25 A25 A25 A25 A25 PE3_GPIO27
EPI0S26 A26 A26 A26 CS0 PH6_GPIO54
EPI0S27 A27 A27 CS1 CS1 PH7_GPIO55
EPI0S30 ALE CS0 CS0 ALE PD7_GPIO23 PJ6_GPIO62
EPI0S29 WR WR WR WR PD6_GPIO22 PJ5_GPIO61
EPI0S28 RD RD RD RD PD5_GPIO21 PJ4_GPIO60
176 Peripheral Information and Timings Copyright © 2012–2014, Texas Instruments Incorporated
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