Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B

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SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014

Table 7-7. EPI MODES – 8-Bit Host-Bus Mode (EPICFG/MODE = 0x2),

Non-Muxed (EPIHB16CFG/MODE = 0x1) (continued)

EPI PORT NAME EPI SIGNAL FUNCTION DEVICE PIN

With With With With

Accessible by Accessible by Address Latch One Two ALE and Two (Available GPIOMUX_1

Cortex-M3 C28x Enable Chip Select Chip Selects Chip Selects Muxing Choices for EPI)

(CSCFG = 0x0) (CSCFG = 0x1) (CSCFG = 0x2) (CSCFG = 0x3)

EPI0S34 x x x x PE4_GPIO28

EPI0S35 x x x x PE5_GPIO29

EPI0S36 x x x x PB7_GPIO15 PC3_GPIO67

EPI0S37 x x x x PB6_GPIO14 PC2_GPIO66

EPI0S38 x x x x PF6_GPIO38 PE4_GPIO28

EPI0S39 x x x x PG2_GPIO42

EPI0S40 x x x x PG5_GPIO45

EPI0S41 x x x x PG6_GPIO46

EPI0S42 x x x x PN6_GPIO102

EPI0S43 x x x x PN7_GPIO103

7.1.4.3.1.3 HB-8 FIFO Mode

The HB-8 FIFO Mode uses 8 bits of data, removes ALE and address pins, and optionally adds external

FIFO Full/Empty flag inputs. This scheme is used by many devices, such as radios, communication

devices (including USB2 devices), and some FPGA configuration (FIFO throughblock RAM). This FIFO

Mode presents the data side of the normal Host-Bus interface, but is paced by FIFO control signals. It is

important to consider that the FIFO Full/Empty control inputs may stall the EPI interface and can

potentially block other CPU or DMA accesses. For more detailed maps of the HB-8 FIFO Mode, see

Table 7-8.

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