Datasheet

GPIO_MUX1
EPI
AHB BUS
M3 BUS
MATRIX
M3
uDMA
HOST BUS INTERFACESDRAM INTERFACEGENERAL PURPOSE INTERFACE
BAUD RATE CONTROL
AHB BUS INTERFACE
EPI MUX
44 PINS
M3 CLOCKS
EPI CLK
M3SYSRST
EPI RST
RESETS
GPIOCSEL REGSDRAM CFG REG GPIOCSEL REGHB-8 CONFIG2 REGGPIOCSEL REGGP CONFIG2 REG
GPIOCSEL REGHB-8 CONFIG REG
8-BIT MODE
GPIOCSEL REG
GPIOCSEL REG
16-BIT MODE
HB-16 CONFIG2 REG
HB-16 CONFIG REG
GPIOCSEL REGGP CONFIG REG
GPIOCSEL REGEPI ADDR MAP REG EPI BAUD REG
READ FIFO CNT REG
FIFO LEVEL SEL REG
EPI CONFIG REG
EPI STATUS REG
READ FIFO REG
8X32 NBR FIFO4X32 WR FIFO
READ FIFO ALIAS 1
READ FIFO ALIAS 2
READ FIFO ALIAS 3
READ FIFO ALIAS 4
READ FIFO ALIAS 5
READ FIFO ALIAS 6
READ FIFO ALIAS 7
C28
CPU
C28
DMA
M3
CPU
APB BUS
RTWEPIREG REG
RTWEPICNTR REG
RTWEPIWD REG
CEPISTATUS REG
MEMPROT REG
MEM32 TO AHB BUS BRIDGE
CONVERTS C28 CPU/DMA BUS
CYCLES TO M3 AHB BUS CYCLES
MEM32
TO AHB
BUS
BRIDGE
FREQ
GASKET
REAL-TIME WINDOW MODE
ALLOWS UN-INTERRUPTED ACCESS
TO EPI FROM C28 CPU/DMA, WHILE
STALLING M3 CPU/DMA CYCLES
THE M3 FREQUENCY GASKET REDUCES AHB
BUS ACCESS FREQUENCY FOR C28 CPU/DMA
CYCLES BY FACTOR OF 2 OR FACTOR OF 4
MEMORY PROTECTION LOGIC ASSIGNS CS
SPACES TO C28 ONLY, M3 ONLY, OR BOTH
NVIC
PIE
WR FIFO CNT REG
EPI REQ
EPI
EPI
CHAN 20
CHAN 22
VECT# 69
INT12/INTx.6
MASK INT STAT REG
ERR INT STAT/CLR
INT MASK REG
RAW INT STAT REG
EPI INTERRUPT
INTERRUPT
SOURCES
EPI RD DATA0 REG
EPI RD ADDR0 REG
EPI RD SIZE0 REG
EPI RD DATA1 REG
EPI NON-BLOCKING
ACCESS REGISTERS
M3SSCLK
EPI RD ADDR0 REG
EPI RD SIZE0 REG
WRITE
FIFO READ
(NON-BLOCKING)
NON-FIFO READ
(BLOCKING)
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
Figure 7-7. EPI
164 Peripheral Information and Timings Copyright © 2012–2014, Texas Instruments Incorporated
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