Datasheet

Interrupt Vector
XNMI, XINT1, XINT2
Address bus
(internal)
t
w(INT)
t
d(INT)
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
6.9 External Interrupt Electrical Data and Timing
Table 6-40. External Interrupt Timing Requirements
(1)
MIN MAX UNIT
t
w(INT)
(2)
Pulse duration, INT input low/high Synchronous 1t
c(SCO)
cycles
With qualifier 1t
c(SCO)
+ t
w(IQSW)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-33.
(2) This timing is applicable to any GPIO pin configured for ADCSOC functionality.
Table 6-41. External Interrupt Switching Characteristics
(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
t
d(INT)
Delay time, INT low/high to interrupt-vector fetch t
w(IQSW)
+ 12t
c(SCO)
cycles
(1) For an explanation of the input qualifier parameters, see Table 6-33.
Figure 6-11. External Interrupt Timing
Copyright © 2012–2014, Texas Instruments Incorporated Electrical Specifications 153
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