Datasheet

XCLKOUT
Address/Data
(internal)
WAKE INT
(A)(B)
t
d(WAKE-IDLE)
t
w(WAKE-INT)
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
6.8.4 Low-Power Mode Wakeup Timing
Table 6-34 shows the timing requirements, Table 6-35 shows the switching characteristics, and Figure 6-8
shows the timing diagram for IDLE mode.
Table 6-34. IDLE Mode Timing Requirements
(1)
MIN MAX UNIT
Without input qualifier 2t
c(SCO)
Pulse duration, external wake-up
t
w(WAKE-INT)
cycles
signal
With input qualifier 5t
c(SCO)
+ t
w(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-33.
Table 6-35. IDLE Mode Switching Characteristics
(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Delay time, external wake signal to program
execution resume
(2)
Wake-up from Flash Without input qualifier 20t
c(SCO)
cycles
• Flash module in active state
With input qualifier 20t
c(SCO)
+ t
w(IQSW)
t
d(WAKE-IDLE)
Wake-up from Flash Without input qualifier 1050t
c(SCO)
cycles
• Flash module in sleep state
With input qualifier 1050t
c(SCO)
+ t
w(IQSW)
Without input qualifier 20t
c(SCO)
cycles
• Wake-up from SARAM
With input qualifier 20t
c(SCO)
+ t
w(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 6-33.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered
by the wake up) signal involves additional latency.
A. WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
B. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be
initiated until at least 4 OSCCLK cycles have elapsed.
Figure 6-8. IDLE Entry and Exit Timing
148 Electrical Specifications Copyright © 2012–2014, Texas Instruments Incorporated
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