Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Table 6-28. Control Subsystem – Flash Parameters at 150 MHz
(1)(2)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
Program Time
(3)
128 bits 180 μs
16K Sector 190 ms
64K Sector 760 ms
Erase Time
(4)
16K Sector 40 ms
64K Sector 40 ms
I
DDP
(5)
V
DD
current consumption during Erase/Program cycle VREG disabled 90 mA
I
DDIOP
(5)
V
DDIO
current consumption during Erase/Program cycle 50
I
DDIOP
(5)
V
DDIO
current consumption during Erase/Program cycle VREG enabled 150 mA
(1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
(2) Before trying to erase or program the C28x Flash, ensure that the Cortex-M3 core does not generate a reset while the C28x Flash is
being erased or programmed.
(3) Program time includes overhead of state machine but does not include data transfer time. Program time assumes programming 144 bits
at a time. Program time includes Program verify by the CPU.
(4) Erase time includes Erase verify by the CPU.
(5) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a
stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure V
MIN
on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during
flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed
during the programming process.
Table 6-29. Control Subsystem – Flash/OTP Access Timing
(1)
PARAMETER MIN MAX UNIT
t
a(f)
Flash access time 25 ns
t
a(OTP)
OTP access time 50 ns
(1) Access time numbers shown in this table are prior to device characterization. Final numbers will be published in the datasheet for the
fully qualified production device.
Table 6-30. Control Subsystem – Flash Data Retention Duration
PARAMETER TEST CONDITIONS MIN MAX UNIT
t
retention
Data retention duration T
J
= 85°C 20 years
Copyright © 2012–2014, Texas Instruments Incorporated Electrical Specifications 143
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