Datasheet
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
6.6 Flash Timing – Master Subsystem
Table 6-16. Master Subsystem – Flash/OTP Endurance for T Temperature Material
(1)
ERASE/PROGRAM
MIN TYP MAX UNIT
TEMPERATURE
N
f
Flash endurance for the array (write/erase cycles) 0°C to 105°C (ambient) 20000 50000 cycles
N
OTP
OTP endurance for the array (write cycles) 0°C to 105°C (ambient) 1 write
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
Table 6-17. Master Subsystem – Flash/OTP Endurance for S Temperature Material
(1)
ERASE/PROGRAM
MIN TYP MAX UNIT
TEMPERATURE
N
f
Flash endurance for the array (write/erase cycles) 0°C to 125°C (ambient) 20000 50000 cycles
N
OTP
OTP endurance for the array (write cycles) 0°C to 125°C (ambient) 1 write
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
Table 6-18. Master Subsystem – Flash/OTP Endurance for Q Temperature Material
(1)
ERASE/PROGRAM
MIN TYP MAX UNIT
TEMPERATURE
N
f
Flash endurance for the array (write/erase cycles) –40°C to 125°C (ambient) 20000 50000 cycles
N
OTP
OTP endurance for the array (write cycles) –40°C to 125°C (ambient) 1 write
(1) Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers.
Table 6-19. Master Subsystem – Flash Parameters at 75 MHz
(1)(2)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
Program Time
(3)
128 bits 280 μs
32K Sector 580 ms
128K Sector 2320 ms
Erase Time 32K Sector 60 ms
128K Sector 60 ms
I
DDP
(4)
V
DD
current consumption during Erase/Program cycle VREG disabled 105 mA
I
DDIOP
(4)
V
DDIO
current consumption during Erase/Program cycle 55
I
DDIOP
(4)
V
DDIO
current consumption during Erase/Program cycle VREG enabled 195 mA
(1) The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required
prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent
programming operations.
(2) Erase time includes Erase verify by the CPU.
(3) Program time includes overhead of state machine but does not include data transfer time. Program time assumes programming 144 bits
at a time. Program time includes Program verify by the CPU.
(4) Typical parameters as seen at room temperature including function call overhead, with all peripherals off. It is important to maintain a
stable power supply during the entire flash programming process. It is conceivable that device current consumption during flash
programming could be higher than normal operating conditions. The power supply used should ensure V
MIN
on the supply rails at all
times, as specified in the Recommended Operating Conditions of the data sheet. Any brown-out or interruption to power during
erasing/programming could potentially corrupt the password locations and lock the device permanently. Powering a target board (during
flash programming) through the USB port is not recommended, as the port may be unable to respond to the power demands placed
during the programming process.
Copyright © 2012–2014, Texas Instruments Incorporated Electrical Specifications 139
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