Datasheet

PLLSYSCLK
BEFORE THE
CHANGE
WRITE TO SYSPLLCTL
REGISTER TO PUT PLL
IN BYPASS MODE
WRITE TO SYSPLLCTL
REGISTER TO TAKE PLL
OUT OF BYPASS MODE
(MINIMUM 2000 OSCCLK CYCLES)
WRITE TO SYSPLLMULT
REGISTGER TO CHANGE PLL
MULTIPLIER CONFIGURATION
STEP 1 STEP 2 STEP 3
10 MHz x 40 =
400 MHz / 2 =
200 MHz / 2 =
100 MHz / 1 =
100 MHz
10 MHz
150 MHz
SPLLIMULT = 40
SPLLFMULT = 2
PLL OUTPUT / 2
SYSDIVSEL = 0
100 MHz
10 MHz
INPUT CLK TO
PLL IS OSCCLK
SYSPLLMULT REG
SYSDIVSEL REG
PLLSYSCLK
DURING THE
CHANGE
10 MHz
100 MHz / 1 =
10 MHz
OSCCLK BYPASSES
THE PLL
PLLSYSCLK
AFTER THE
CHANGE
10 MHz x 60 =
600MHz / 2 =
300 MHz / 2 =
150 MHz / 1 =
150 MHz
10 MHz
INPUT CLK TO
PLL IS OSCCLK
SYSPLLMULT REG
SYSDIVSEL REG
SPLLIMULT = 60
SPLLFMULT = 2
PLL OUTPUT / 2
SYSDIVSEL = 0
PLLSYSCLK
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
6.5.1 Changing the Frequency of the Main PLL
Figure 6-4 shows how to change the frequency of the Main PLL. The three steps are described below:
1. The PLL must first be placed in bypass mode (by writing to the SYSPLLCTL register) before any
changes are made to the SPLLIMULT and SPLLFMULT fields of the SYSPLLMULT Register. Figure 6-
4 shows that before being placed in bypass mode, the internal PLLSYSCLK clock was operating at
100 MHz. After entering the bypass mode, the PLLSYSCLK becomes 10 MHz, which is the frequency
of OSCCLK, the input clock to the PLL
2. Once the PLL is placed in bypass mode, the SYSPLLMULT register can be modified to increase the
PLLSYSCLK frequency to 150 MHz. See Figure 6-4 for the settings of the SPLLIMULT (integer) and
SPLLFMULT (fractional) multiply fields of the SYSPLLMULT register for this step, and see Figure 3-8
for the functional description of the Main PLL. The PLL bypass mode must be maintained for at least
2000 OSCCLK cycles in order for the PLL to properly lock to the new frequency.
3. Finally, the SYSPLLCTL register is written to again, this time to take the PLL out of the bypass mode.
Following this step, the PLLSYSCLK switches over from 10 MHz to the new frequency of 150 MHz.
Figure 6-4. Changing the Frequency of the Main PLL
Copyright © 2012–2014, Texas Instruments Incorporated Electrical Specifications 137
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