Datasheet

t
h(boot-mode)
(A)
t
w(RSL2)
X1/X2
XRS
Boot-Mode
Pins
XCLKOUT
I/O Pins
Address/Data/
Control
(Internal)
Boot-ROM Execution Starts
User-Code Execution Starts
User-Code Dependent
User-Code Execution Phase
User-Code Dependent
User-Code Execution
Peripheral/GPIO Function
User-Code Dependent
GPIO Pins as Input (State Depends on Internal PU/PD)
GPIO Pins as Input
Peripheral/GPIO Function
t
d(EX)
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
Table 6-13. Reset (XRS) Timing Requirements
MIN MAX UNIT
t
h(boot-mode)
Hold time for boot-mode pins 14000t
c(M3C)
cycles
t
w(RSL2)
Pulse duration, XRS low on warm reset 32t
c(OCK)
cycles
Table 6-14. Reset (XRS) Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN TYP MAX UNIT
t
w(RSL1)
Pulse duration, XRS driven by device 600 μs
t
w(WDRS)
Pulse duration, reset pulse generated by watchdog 512t
c(OCK)
cycles
t
d(EX)
Delay time, address/data valid after XRS high 32t
c(OCK)
cycles
t
INTOSCST
Start up time, internal zero-pin oscillator 3 μs
t
OSCST
(1)
On-chip crystal-oscillator start-up time 1 10 ms
(1) Dependent on crystal/resonator and board design.
A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code
branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in
debugger environment), the Boot code execution time is based on the current M3SSCLK speed. The M3SSCLK will
be based on user environment and could be with or without PLL enabled.
Figure 6-3. Warm Reset
136 Electrical Specifications Copyright © 2012–2014, Texas Instruments Incorporated
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Product Folder Links: F28M36P63C F28M36P53C F28M36H53C F28M36H53B F28M36H33C F28M36H33B