Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
5.3 Recommended Operating Conditions
MIN NOM MAX UNIT
Device supply voltage, I/O, V
DDIO
(1)
2.97 3.3 3.63 V
Device supply voltage, Analog Subsystem, V
DD18
1.71 1.8 1.995
(when internal VREG is disabled and 1.8 V is V
supplied externally)
Device supply voltage, Master and Control 1.14 1.2 1.32
Subsystems, V
DD12
V
(when internal VREG is disabled and 1.2 V is
supplied externally)
Supply ground, V
SS
0 V
Analog supply voltage, V
DDA
(1)
2.97 3.3 3.63 V
Analog ground, V
SSA
0 V
Device clock frequency (system clock) P63C, P53C 2 125
MHz
Master Subsystem
H53C, H53B, H33C, H33B 2 100
Device clock frequency (system clock) 2 150
MHz
Control Subsystem
High-level input voltage, V
IH
(3.3 V) V
DDIO
* 0.7 V
DDIO
+ 0.3 V
Low-level input voltage, V
IL
(3.3 V) V
SS
– 0.3 V
DDIO
* 0.3 V
High-level output source current, V
OH
= V
OH(MIN)
, I
OH
All GPIO/AIO pins –4 mA
Group 2
(2)
–8 mA
Low-level output sink current, V
OL
= V
OL(MAX)
, I
OL
All GPIO/AIO pins 4 mA
Group 2
(2)
8 mA
Free-Air temperature, T
A
T version –40 105
S version –40 125 °C
Q version (Q100 qualification) –40 125
Junction temperature, T
J
T version –40 125
S version –40 150 °C
Q version (Q100 qualification) –40 150
(1) V
DDIO
and V
DDA
should be maintained within approximately 0.3 V of each other.
(2) Group 2 pins are as follows: PD3_GPIO19, PE2_GPIO26, PE3_GPIO27, PH6_GPIO54, PH7_GPIO55, EMU0, TDO, EMU1,
PD0_GPIO16, AIO7, AIO4.
124 Device Operating Conditions Copyright © 2012–2014, Texas Instruments Incorporated
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