Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Table 4-1. Terminal Functions
(1)
(continued)
TERMINAL
PU OUTPUT
I/O/Z
(2)
DESCRIPTION or BUFFER
ZWT
NAME
PD
(3)
STRENGTH
BALL NO.
Digital Logic Power Pins (Master and Control Subsystems)
V
DD12
M7
V
DD12
M13
1.2-V Digital Logic Power Pins - no supply needed
V
DD12
N7
when using internal VREG12. Tie with 250-nF
V
DD12
N12
(minimum) to 750-nF (maximum) ceramic
capacitor (10% tolerance) to ground when using
V
DD12
N13
internal VREG. Higher value capacitors may be
V
DD12
T10
used but could impact supply-rail ramp-up time.
V
DD12
T11
V
DD12
T12
Digital Logic Ground (Analog, Master, and Control Subsystems)
V
SS
A1
V
SS
A2
V
SS
A18
V
SS
A19
V
SS
B1
V
SS
B19
V
SS
D6
V
SS
D14
V
SS
E4
V
SS
E16
V
SS
H8
V
SS
H9
V
SS
H10
V
SS
H11
V
SS
H12 Digital Ground
V
SS
J4
V
SS
J8
V
SS
J9
V
SS
J10
V
SS
J11
V
SS
J12
V
SS
J16
V
SS
K4
V
SS
K8
V
SS
K9
V
SS
K10
V
SS
K11
V
SS
K12
V
SS
K16
Copyright © 2012–2014, Texas Instruments Incorporated Terminal Description 121
Submit Documentation Feedback
Product Folder Links: F28M36P63C F28M36P53C F28M36H53C F28M36H53B F28M36H33C F28M36H33B