Datasheet
F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
www.ti.com
Table 4-1. Terminal Functions
(1)
(continued)
TERMINAL
PU OUTPUT
I/O/Z
(2)
DESCRIPTION or BUFFER
ZWT
NAME
PD
(3)
STRENGTH
BALL NO.
Digital Logic Power Pins for I/Os, Flash, USB, and Internal Oscillators
V
DDIO
D4
V
DDIO
D5
V
DDIO
D15
V
DDIO
D16
V
DDIO
G7
V
DDIO
G13
V
DDIO
G8
V
DDIO
G9
V
DDIO
G10
V
DDIO
G11
V
DDIO
G12
V
DDIO
H7
V
DDIO
H13
3.3-V Digital I/O and FLASH Power Pin. Tie with a
V
DDIO
J7
0.1-µF capacitor (typical) close to the pin. When
the 1.2-V VREG is enabled (by pulling the
V
DDIO
J13
VREG12EN pin low), these pins also supply
V
DDIO
N8
power to the Digital Subsystem. When the 1.8-V
V
DDIO
N9
VREG is enabled (by pulling the VREG18EN pin
low), these pins also supply power to the Analog
V
DDIO
N10
Subsystem.
V
DDIO
N11
V
DDIO
K7
V
DDIO
L7
V
DDIO
K13
V
DDIO
L13
V
DDIO
T4
V
DDIO
T5
V
DDIO
T7
V
DDIO
T8
V
DDIO
T15
V
DDIO
T16
V
DDIO
T13
V
DDIO
U13
Digital Logic Power Pins (Analog Subsystem)
V
DD18
C7 1.8-V Digital Logic Power Pins (associated with
the Analog Subsystem) - no supply needed when
V
DD18
D7
using internal VREG18. Tie with 1.2-µF (minimum)
V
DD18
D12
ceramic capacitor (10% tolerance) to ground when
using internal VREG. Higher value capacitors may
V
DD18
D13
be used but could impact supply-rail ramp-up time.
120 Terminal Description Copyright © 2012–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: F28M36P63C F28M36P53C F28M36H53C F28M36H53B F28M36H33C F28M36H33B