Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Table 4-1. Terminal Functions
(1)
(continued)
TERMINAL
PU OUTPUT
I/O/Z
(2)
DESCRIPTION or BUFFER
ZWT
NAME
PD
(3)
STRENGTH
BALL NO.
ITM Trace (ARM Instrumentation Trace Macrocell)
see
TRACED0 O ITM Trace data 0 4 mA
PF3_GPIO35
see
TRACED1 O ITM Trace data 1 4 mA
PG3_GPIO43
see
TRACED2 O ITM Trace data 2 4 mA
PF0_GPIO32
see
TRACED3 O ITM Trace data 3 4 mA
PF1_GPIO33
see
TRACECLK O ITM Trace clock 4 mA
PF2_GPIO34
Test Pins
FLASH Test Pin 1. Reserved for TI. Must be left
FLT1 K1 I/O
unconnected.
FLASH Test Pin 2. Reserved for TI. Must be left
FLT2 L1 I/O
unconnected.
Internal Voltage Regulator Control
Internal 1.8-V VREG Enable/Disable for V
DD18
.
VREG18EN A15 Pull low to enable the internal 1.8-V voltage PD
regulator (VREG18), pull high to disable VREG18.
Internal 1.2-V VREG Enable/Disable for V
DD12
.
VREG12EN E19 Pull low to enable the internal 1.2-V voltage PD
regulator (VREG12), pull high to disable VREG12.
Copyright © 2012–2014, Texas Instruments Incorporated Terminal Description 119
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