Datasheet

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F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B

SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014

www.ti.com

Table 4-1. Terminal Functions

(1)

(continued)

TERMINAL

PU OUTPUT

I/O/Z

(2)

DESCRIPTION or BUFFER

ZWT

NAME

(3)

STRENGTH

BALL NO.

JTAG test data input (TDI) with internal pullup.

TDI K19 I TDI is clocked into the selected register PU

(instruction or data) on a rising edge of TCK.

JTAG scan out, test data output (TDO). The

contents of the selected register (instruction or

TDO T19 O 4 mA

data) are shifted out of TDO on the falling edge of

TCK.

Emulator pin 0. When TRST is driven high, this

pin is used as an interrupt to or from the emulator

system and is defined as input/output through the

JTAG scan. This pin is also used to put the device

into boundary-scan mode. With the EMU0 pin at a

logic-high state and the EMU1 pin at a logic-low

state, a rising edge on the TRST pin would latch

the device into boundary-scan mode.

NOTE: An external pullup resistor is required on

this pin. The value of this resistor should be based

EMU0 P19 I/O/Z on the drive strength of the debugger pods PU 4 mA

applicable to the design. A 2.2-kΩ to 4.7-kΩ

resistor is generally adequate. Since the value of

the resistor is application-specific, TI recommends

that each target board be validated for proper

operation of the debugger and the application.

NOTE: If EMU0 is 0 and EMU1 is 1 when coming

out of reset, the device enters Wait-in-Reset

mode. WIR suspends bootloader execution,

allowing the Emulator to connect to the device and

to modify FLASH contents.

Emulator pin 1. When TRST is driven high, this