Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
www.ti.com SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014
Table 4-1. Terminal Functions
(1)
(continued)
TERMINAL
PU OUTPUT
I/O/Z
(2)
DESCRIPTION or BUFFER
ZWT
NAME
PD
(3)
STRENGTH
BALL NO.
Clocks
External oscillator input or on-chip crystal-
oscillator input. To use the on-chip oscillator, a
X1 J19 I
quartz crystal or a ceramic resonator must be
connected across X1 and X2. See Figure 3-7.
On-chip crystal-oscillator output. A quartz crystal
or a ceramic resonator must be connected across
X2 G19 O
X1 and X2. If X2 is not used, it must be left
unconnected. See Figure 3-7.
Clock Oscillator Ground Pin. Use this pin to
connect the GND of external crystal load
V
SSOSC
H18 capacitors or the ground pin of 3-terminal ceramic
resonators with built-in capacitors. Do not connect
to board ground. See Figure 3-7.
Clock Oscillator Ground Pin. Use this pin to
connect the GND of external crystal load
V
SSOSC
H19 capacitors or the ground pin of 3-terminal ceramic
resonators with built-in capacitors. Do not connect
to board ground. See Figure 3-7.
External oscillator input. This pin feeds a clock
see
XCLKIN I from an external 3.3-V oscillator to internal USB
PJ7_GPIO63
PLL module and to the CAN peripherals.
External oscillator output. This pin outputs a clock
see divided-down from the internal PLL System Clock.
XCLKOUT O/Z
PF2_GPIO34 The divide ratio is defined in the XPLLCLKCFG
register.
Boot Pins
One of four boot mode pins. BOOT_0 selects a
see
BOOT_0 I specific configuration source from which the PU
PG3_GPIO43
Concerto device boots on start-up.
One of four boot mode pins. BOOT_1 selects a
see
BOOT_1 I specific configuration source from which the PU
PG7_GPIO47
Concerto device boots on start-up.
One of four boot mode pins. BOOT_2 selects a
see
BOOT_2 I specific configuration source from which the PU
PF3_GPIO35
Concerto device boots on start-up.
One of four boot mode pins. BOOT_3 selects a
see
BOOT_3 I specific configuration source from which the PU
PF2_GPIO34
Concerto device boots on start-up.
JTAG
JTAG test reset with internal pulldown. TRST,
when driven high, gives the scan system control of
the operations of the device. If this signal is not
connected or driven low, the device operates in its
functional mode, and the test reset signals are
ignored. NOTE: TRST is an active-low test pin
and must be maintained low during normal device
operation. An external pull-down resistor is
TRST N19 I PD
required on this pin. The value of this resistor
should be based on drive strength of the debugger
pods applicable to the design. A 2.2-kΩ resistor
generally offers adequate protection. Since the
value of the resistor is application-specific, TI
recommends that each target board be validated
for proper operation of the debugger and the
application.
TCK L19 I JTAG test clock
JTAG test-mode select (TMS) with internal pullup.
TMS M19 I This serial control input is clocked into the TAP PU
controller on the rising edge of TCK.
Copyright © 2012–2014, Texas Instruments Incorporated Terminal Description 117
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