Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
Table 4-1. Terminal Functions
(1)
(continued)
TERMINAL
PU OUTPUT
I/O/Z
(2)
DESCRIPTION or BUFFER
ZWT
NAME
PD
(3)
STRENGTH
BALL NO.
Resets
Digital Subsystem Reset (in) and
Watchdog/Power-on Reset (out). In most
applications, TI recommends that the XRS pin be
tied with the ARS pin. The Digital Subsystem has
a built-in POR circuit, and during a power-on
condition, this pin is driven low by the Digital
Subsystem. This pin is also driven low by the
Digital Subsystem when a watchdog reset occurs.
During watchdog reset, the XRS pin is driven low
for the watchdog reset duration of 512 OSCCLK
cycles. If need be, an external circuitry may also
drive this pin to assert device reset. In this case,
XRS C1 I/OD PU 4 mA
TI recommends that this pin be driven by an open-
drain device. An R-C circuit must be connected to
this pin for noise immunity reasons. Regardless of
the source, a device reset causes the Digital
Subsystem to terminate execution. The Cortex-M3
program counter points to the address contained
at the location 0x00000004. The C28 program
counter points to the address contained at the
location 0x3FFFC0. When reset is deactivated,
execution begins at the location designated by the
program counter. The output buffer of this pin is
an open-drain with an internal pullup.
Analog Subsystem Reset (in) and Power-on Reset
(out).In most applications, TI recommends that the
ARS pin be tied with the XRS pin. The Analog
Subsystem has a built-in POR circuit, and during a
power-on condition, this pin is driven low by the
Analog Subsystem. If need be, external circuitry
may also drive this pin to assert a device reset. In
ARS A3 I/OD this case, TI recommends that this pin be driven PU 4 mA
by an open-drain device. An R-C circuit must be
connected to this pin for noise immunity reasons.
Regardless of the source, the Analog Subsystem
reset causes the digital logic associated with the
Analog Subsystem, to enter reset state. The
output buffer of this pin is an open-drain with an
internal pullup.
116 Terminal Description Copyright © 2012–2014, Texas Instruments Incorporated
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