Datasheet

F28M36P63C, F28M36P53C, F28M36H53C, F28M36H53B, F28M36H33C, F28M36H33B
SPRS825C –OCTOBER 2012–REVISED FEBRUARY 2014 www.ti.com
Table 4-1. Terminal Functions
(1)
(continued)
TERMINAL
PU OUTPUT
I/O/Z
(2)
DESCRIPTION or BUFFER
ZWT
NAME
PD
(3)
STRENGTH
BALL NO.
PH3_GPIO51 I/O/Z General-purpose input/output 51
USB-0 external power enable
M_USB0EPEN O
(optionally used in the host mode)
M_EPI0S0 I/O EPI-0 signal 0
U7 PU 4 mA
M_MIITXD2 O EMAC MII transmit data 2
M_SSI3FSS I/O SSI-3 frame
M_MIITXD0 O EMAC MII transmit data 0
C_EQEP1B I Enhanced QEP-1 input B
PH4_GPIO52 I/O/Z General-purpose input/output 52
USB-0 external power error state
M_USB0PFLT I
(optionally used in the host mode)
M_EPI0S10 I/O EPI-0 signal 10
M_MIITXD1 O EMAC MII transmit data 1
U10 PU 4 mA
M_SSI1CLK I/O SSI-1 clock
M_U3TX O UART-3 transmit data
M_MIICOL I EMAC MII collision detect
C_EQEP1S I/O Enhanced QEP-1 strobe
PH5_GPIO53 I/O/Z General-purpose input/output 53
M_EPI0S11 I/O EPI-0 signal 11
M_MIITXD0 O EMAC MII transmit data 0
M_SSI1FSS U9 I/O SSI-1 frame PU 4 mA
M_U3RX I UART-3 receive data
M_MIIPHYRST O EMAC PHY MII reset
C_EQEP1I I/O Enhanced QEP-1 index
PH6_GPIO54 I/O/Z General-purpose input/output 54
M_EPI0S26 I/O EPI-0 signal 26
M_MIIRXDV I EMAC MII receive data valid
M_SSI1RX I SSI-1 receive data
M_MIITXEN R17 O EMAC MII transmit enable PU 4 mA
M_SSI0TX O SSI-0 transmit data
M_MIIPHYINTR I EMAC PHY MII interrupt
C_SPISIMOA I/O SPI-A slave in, master out
C_EQEP3A I Enhanced QEP-1 input A
PH7_GPIO55 I/O/Z General-purpose input/output 55
M_MIIRXCK I EMAC MII receive clock
M_EPI0S27 I/O EPI-0 signal 27
M_SSI1TX O SSI-1 transmit data
M_MIITXCK P18 I EMAC MII transmit clock PU 4 mA
M_SSI0RX I SSI-0 receive data
M_MIIMDC O EMAC management data clock
C_SPISOMIA I/O SPI-A master in, slave out
C_EQEP3B I Enhanced QEP-3 input B
108 Terminal Description Copyright © 2012–2014, Texas Instruments Incorporated
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