Datasheet

Clock

Prescale

TBPRDSYSCLKOUT

TBCLK

EPWMxSOCA

/ETPS ADC

PWM

FREQ

/ISRvsCTRL

ISR

/CTRLvsEST

/CTRLvsCURRENT

/CTRLvsSPEED

/CTRLvsTRAJ

CTRL

EST

CURRENT

SPEED

TRAJ

Software Decimation

Hardware Decimation

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Microcontroller Resources

InstaSPIN-FOC provides flexibility throughout its design, including its software execution clock tree.

Figure 5 illustrates the options available to the designer to manage the real-time scheduling of each of the

major software functions. Balancing motor performance with CPU loading is not difficult, shortening

system integration time.

Figure 5. Software Execution Clock Tree Provides Flexibility with Real-Time Scheduling

Executing from a combination of single-cycle memory (RAM and ROM) and also from FLASH, total

execution time for the minimum full implementation of InstaSPIN-FOC depends on the software execution

clock tree. Table 2 shows the CPU cycles used when a minimum full implementation of InstaSPIN is done,

as well as users' code is loaded to FLASH. Note the impact of the software execution tree to total

execution time. Table 3 shows the CPU loading and available MIPs for other system functions.

Table 2. CPU Cycles for MIN Implementation Executing from ROM, RAM, and FLASH

CPU Cycles Executed From

Function Name Min Average Max ROM RAM FLASH

DRV_acqAdcInt 17 17 17 × ✓ ×

DRV_readAdcData 94 94 94 × ✓ ×

SPRUHP4–August 2013 TMS320F28026F, TMS320F28027F InstaSPIN™-FOC Software

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